dmgreen added a comment.

Thanks for your comments. This patch is not intended to have no consequence - 
it's just not being communicated well in the commit message.

The problem at the moment, with mainline clang, is that specifying:

  #pragma clang loop vectorize_width(4) vectorize_predicate(enable)

(or under MVE, as predication is often done by default):

  #pragma clang loop vectorize_width(4) vectorize_predicate(disable)

The predication is ignored because the width is set. As in:
https://godbolt.org/z/ex8jvW
So there is no way at the moment to control predication and width at the same 
time.

That is what this patch is aiming to fix, and that fix alone is quite simple. 
Unfortunately in order to fix that we also need to deal with (like you say) the 
awkward edge case where vectorize_width(1) is set and predication is enabled. 
But that's really just an edge case. This patch makes it work similar to 
interleaving, as far as I understand. If the user specifies

  #pragma clang loop vectorize_width(1) interleave_count(4) 
vectorize_predicate(enable)

They get no vectorization, but interleaving which is predicated. I.e what they 
asked for. (There's a chance that is then SLP vectorizes, but that's a 
different problem :-) ) The predicated interleaving will likely be horrible for 
performance, but if the user asked for it I don't see a reason not to give it 
to them in this case. And the more interesting case of when a vector width is 
specified should start working. The only thing that is really changing is when 
llvm.loop.vectorize.predicate.enable is emitted, and I only meant to imply for 
the predicate pragma specifically, that the user should get what they ask for 
so long as the vectorizer can provide it.

I agree with you in general that pragmas/metadata are difficult and should not 
be changed without good reason.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94779/new/

https://reviews.llvm.org/D94779

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