rsanthir.quic marked 2 inline comments as done.
rsanthir.quic added a comment.
Thank you for taking a look at this @labrinea !
================
Comment at: llvm/test/CodeGen/AArch64/neon-sm4-sm3.ll:77
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sm4e v1.4s, v0.4s
+; CHECK-NEXT: mov v0.16b, v1.16b
----------------
labrinea wrote:
> Shouldn't the registers be the other way around: sm4e v0.4s, v1.4s ? I
> believe the reason this happens is because of how CryptoRRTied is defined in
> `llvm/lib/Target/AArch64/AArch64InstrFormats.td`:
>
>
> ```
> class CryptoRRTied<bits<1>op0, bits<2>op1, string asm, string asmops>
> : BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm), asm, asmops,
> "$Vm = $Vd", []> {
> ```
>
> Vd be should be the first source register (as well as destination register)
> and Vn should be the second source register.
I see what you mean, this has the added effect of correcting SHA512SU0 as well
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D95655/new/
https://reviews.llvm.org/D95655
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