labrinea added inline comments.
================
Comment at: llvm/test/CodeGen/AArch64/neon-sm4-sm3.ll:24
+
+define <4 x i32> @test_vsm3ss1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x
i32> %d) {
+; CHECK-LABEL: test_vsm3ss1:
----------------
The forth argument (<4 x i32> %d) is redundant.
================
Comment at: llvm/test/CodeGen/AArch64/neon-sm4-sm3.ll:77
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sm4e v1.4s, v0.4s
+; CHECK-NEXT: mov v0.16b, v1.16b
----------------
Shouldn't the registers be the other way around: sm4e v0.4s, v1.4s ? I believe
the reason this happens is because of how CryptoRRTied is defined in
`llvm/lib/Target/AArch64/AArch64InstrFormats.td`:
```
class CryptoRRTied<bits<1>op0, bits<2>op1, string asm, string asmops>
: BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm), asm, asmops,
"$Vm = $Vd", []> {
```
Vd be should be the first source register (as well as destination register) and
Vn should be the second source register.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D95655/new/
https://reviews.llvm.org/D95655
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
