Author: Joe Ellis Date: 2020-12-15T17:19:16Z New Revision: 5a2a8369e82cea9689b0ff60f3e9baa7fc79fbcf
URL: https://github.com/llvm/llvm-project/commit/5a2a8369e82cea9689b0ff60f3e9baa7fc79fbcf DIFF: https://github.com/llvm/llvm-project/commit/5a2a8369e82cea9689b0ff60f3e9baa7fc79fbcf.diff LOG: [AArch64][NEON] Remove undocumented vceqz{,q}_p16, vml{a,s}q_n_f64 intrinsics Prior to this patch, Clang supported the following C/C++ intrinsics: vceqz_p16 vceqzq_p16 vmlaq_n_f64 vmlsq_n_f64 ... exposed through arm_neon.h. However, these intrinsics are not part of the ACLE, allowing developers to write code that is not compatible with other toolchains. This patch removes these intrinsics. There is a bug report capturing this issue here: https://bugs.llvm.org/show_bug.cgi?id=47471 Reviewed By: bsmith Differential Revision: https://reviews.llvm.org/D93206 Added: Modified: clang/include/clang/Basic/arm_neon.td clang/test/CodeGen/aarch64-neon-fma.c clang/test/CodeGen/aarch64-neon-misc.c Removed: ################################################################################ diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td index 4d4e42dd514b..6f1380d58c16 100644 --- a/clang/include/clang/Basic/arm_neon.td +++ b/clang/include/clang/Basic/arm_neon.td @@ -786,9 +786,6 @@ def VMUL_N_A64 : IOpInst<"vmul_n", "..1", "Qd", OP_MUL_N>; def FMLA_N : SOpInst<"vfma_n", "...1", "dQd", OP_FMLA_N>; def FMLS_N : SOpInst<"vfms_n", "...1", "fdQfQd", OP_FMLS_N>; -def MLA_N : SOpInst<"vmla_n", "...1", "Qd", OP_MLA_N>; -def MLS_N : SOpInst<"vmls_n", "...1", "Qd", OP_MLS_N>; - //////////////////////////////////////////////////////////////////////////////// // Logical operations def BSL : SInst<"vbsl", ".U..", "dPlQdQPl">; @@ -868,7 +865,7 @@ def CFMGT : SOpInst<"vcgt", "U..", "lUldQdQlQUl", OP_GT>; def CFMLT : SOpInst<"vclt", "U..", "lUldQdQlQUl", OP_LT>; def CMEQ : SInst<"vceqz", "U.", - "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">; + "csilfUcUsUiUlPcPlQcQsQiQlQfQUcQUsQUiQUlQPcdQdQPl">; def CMGE : SInst<"vcgez", "U.", "csilfdQcQsQiQlQfQd">; def CMLE : SInst<"vclez", "U.", "csilfdQcQsQiQlQfQd">; def CMGT : SInst<"vcgtz", "U.", "csilfdQcQsQiQlQfQd">; diff --git a/clang/test/CodeGen/aarch64-neon-fma.c b/clang/test/CodeGen/aarch64-neon-fma.c index c2dd315ed9fc..0726218d2e15 100644 --- a/clang/test/CodeGen/aarch64-neon-fma.c +++ b/clang/test/CodeGen/aarch64-neon-fma.c @@ -26,16 +26,6 @@ float32x4_t test_vmlaq_n_f32(float32x4_t a, float32x4_t b, float32_t c) { return vmlaq_n_f32(a, b, c); } -// CHECK-LABEL: define <2 x double> @test_vmlaq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 { -// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0 -// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1 -// CHECK: [[MUL_I:%.*]] = fmul <2 x double> %b, [[VECINIT1_I]] -// CHECK: [[ADD_I:%.*]] = fadd <2 x double> %a, [[MUL_I]] -// CHECK: ret <2 x double> [[ADD_I]] -float64x2_t test_vmlaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) { - return vmlaq_n_f64(a, b, c); -} - // CHECK-LABEL: define <4 x float> @test_vmlsq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 { // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %c, i32 1 @@ -58,16 +48,6 @@ float32x2_t test_vmls_n_f32(float32x2_t a, float32x2_t b, float32_t c) { return vmls_n_f32(a, b, c); } -// CHECK-LABEL: define <2 x double> @test_vmlsq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 { -// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0 -// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1 -// CHECK: [[MUL_I:%.*]] = fmul <2 x double> %b, [[VECINIT1_I]] -// CHECK: [[SUB_I:%.*]] = fsub <2 x double> %a, [[MUL_I]] -// CHECK: ret <2 x double> [[SUB_I]] -float64x2_t test_vmlsq_n_f64(float64x2_t a, float64x2_t b, float64_t c) { - return vmlsq_n_f64(a, b, c); -} - // CHECK-LABEL: define <2 x float> @test_vmla_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 { // CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> diff --git a/clang/test/CodeGen/aarch64-neon-misc.c b/clang/test/CodeGen/aarch64-neon-misc.c index 88020a1a69c2..5517fe3dc411 100644 --- a/clang/test/CodeGen/aarch64-neon-misc.c +++ b/clang/test/CodeGen/aarch64-neon-misc.c @@ -198,24 +198,6 @@ uint8x16_t test_vceqzq_p8(poly8x16_t a) { return vceqzq_p8(a); } -// CHECK-LABEL: @test_vceqz_p16( -// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> -// CHECK: [[TMP1:%.*]] = icmp eq <4 x i16> %a, zeroinitializer -// CHECK: [[VCEQZ_I:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16> -// CHECK: ret <4 x i16> [[VCEQZ_I]] -uint16x4_t test_vceqz_p16(poly16x4_t a) { - return vceqz_p16(a); -} - -// CHECK-LABEL: @test_vceqzq_p16( -// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> -// CHECK: [[TMP1:%.*]] = icmp eq <8 x i16> %a, zeroinitializer -// CHECK: [[VCEQZ_I:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16> -// CHECK: ret <8 x i16> [[VCEQZ_I]] -uint16x8_t test_vceqzq_p16(poly16x8_t a) { - return vceqzq_p16(a); -} - // CHECK-LABEL: @test_vceqzq_f64( // CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = fcmp oeq <2 x double> %a, zeroinitializer _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
