LuoYuanke added a comment. In D91927#2412557 <https://reviews.llvm.org/D91927#2412557>, @craig.topper wrote:
> I only took a quick pass through this so far. What happens if a bitcast > between x86amx and v256i32(or any other 1024-bit vector type) exists in the > IR but isn't next to a load/store? @craig.topper , thank you for reviewing my patch. I think if user just use our external API, such IR won't be generated. However if there is such IR, we can transform bitcast to <store, load>, so that the type can be translated through memory. One of <store, load> is AMX intrinsics store/load, so it won't be optimized. Is it reasonable? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91927/new/ https://reviews.llvm.org/D91927 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
