shchenz added a comment. Using dform with offset 0 can save one register r0/X0, this is benefit for register allocation? But adding it in `PPCPreEmitPeephole` pass which is after register allocation will make the benefit gone. Maybe we need to do it before register allocation? For example at the place where the x-form with zero register is generated.
I checked one example `loadConstant` in `test/CodeGen/PowerPC/f128-passByValue.ll`. We generate `LXVX $zero8, ` in ISEL because we meet the worst case and we don't have d-form choice for the instruction selection. so we have to use x-form and in x-form selection, we have to use zero/zero8 as the base and use load address as the index. See `PPCTargetLowering::SelectAddressRegRegOnly`. I guess most cases are with same reason for generating x-form + zero register, we meet the worst case in ISEL, so we have to use x-form + zero register form, with this form, we can always select a powerpc load/store instruction. For me, a better solution should be change the worst case handling in ISEL, it is before RA and it is also transparent for types like STXVX/LXVX/ and also LDX/STDX, LFDX/STFDX... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91279/new/ https://reviews.llvm.org/D91279 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
