ZarkoCA created this revision.
ZarkoCA added reviewers: Xiangling_L, cebowleratibm, sfertile.
Herald added subscribers: llvm-commits, cfe-commits, dang, dmgreen, arphaman,
kbarton, hiraditya, nemanjai.
Herald added projects: clang, LLVM.
ZarkoCA requested review of this revision.
Added support for the options mvecnvol and mnovecnvol which are analogous to
qvecnvol and qnovecnvol when using XL on AIX.
The extended Altivec ABI on AIX is enabled using mvecnvol in clang and vecnvol
in llc.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D89684
Files:
clang/docs/ClangCommandLineReference.rst
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Basic/DiagnosticDriverKinds.td
clang/include/clang/Driver/Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/altivec.c
llvm/include/llvm/CodeGen/CommandFlags.h
llvm/include/llvm/Target/TargetMachine.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/CommandFlags.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
llvm/test/CodeGen/PowerPC/aix-default-vec-abi.ll
llvm/test/CodeGen/PowerPC/aix-func-align.ll
llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
llvm/test/CodeGen/PowerPC/aix-internal.ll
llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
llvm/test/CodeGen/PowerPC/aix-return55.ll
llvm/test/CodeGen/PowerPC/aix-space.ll
llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
llvm/test/CodeGen/PowerPC/aix32-crsave.mir
llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
Index: llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
===================================================================
--- llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -7,7 +7,7 @@
# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -vecnvol \
# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
Index: llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
+++ llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -vecnvol \
; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
@a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
+++ llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
@a = common global i32 0
Index: llvm/test/CodeGen/PowerPC/aix32-crsave.mir
===================================================================
--- llvm/test/CodeGen/PowerPC/aix32-crsave.mir
+++ llvm/test/CodeGen/PowerPC/aix32-crsave.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 -vecnvol \
# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
# RUN: FileCheck %s --check-prefixes=CHECK
Index: llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
@@ -1,12 +1,12 @@
; This file tests TOC entry generation and undefined symbol generation.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64 %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
-; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
+; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
; RUN: < %s | FileCheck --check-prefix=XCOFF64 %s
; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
Index: llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECK %s
define i32 @foo() #0 {
Index: llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -filetype=obj -code-model=large -o %t.o < %s
; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC %s
; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
Index: llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
@@ -3,12 +3,12 @@
; the test in this file should be merged into aix-xcoff-data.ll with additional
; tests for XCOFF object files.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 \
-; RUN: -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 \
-; RUN: -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s
-
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol \
+; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol \
+; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
+; RUN: -data-sections=false -filetype=obj -o %t.o < %s
; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
@magic16 = private unnamed_addr constant [4 x i16] [i16 264, i16 272, i16 213, i16 0], align 2
@@ -25,25 +25,22 @@
ret i8 %1
}
-; CHECK: .csect .rodata.str2.2[RO],2
-; CHECK-NEXT: .align 1
-; CHECK-NEXT: L..magic16:
-; CHECK-NEXT: .vbyte 2, 264 # 0x108
-; CHECK-NEXT: .vbyte 2, 272 # 0x110
-; CHECK-NEXT: .vbyte 2, 213 # 0xd5
-; CHECK-NEXT: .vbyte 2, 0 # 0x0
-; CHECK-NEXT: .csect .rodata.str4.4[RO],2
-; CHECK-NEXT: .align 2
-; CHECK-NEXT: L..magic32:
-; CHECK-NEXT: .vbyte 4, 464 # 0x1d0
-; CHECK-NEXT: .vbyte 4, 472 # 0x1d8
-; CHECK-NEXT: .vbyte 4, 413 # 0x19d
-; CHECK-NEXT: .vbyte 4, 0 # 0x0
-; CHECK-NEXT: .csect .rodata.str1.1[RO],2
-; CHECK-NEXT: L..strA:
-; CHECK-NEXT: .byte 'h,'e,'l,'l,'o,' ,'w,'o,'r,'l,'d,'!,0012,0000
-; CHECK-NEXT: L...str:
-; CHECK-NEXT: .byte 'a,'b,'c,'d,'e,'f,'g,'h,0000
+; CHECK: .csect .rodata.str2.2L..magic16[RO],2
+; CHECK-NEXT: .align 1
+; CHECK-NEXT: .vbyte 2, 264 # 0x108
+; CHECK-NEXT: .vbyte 2, 272 # 0x110
+; CHECK-NEXT: .vbyte 2, 213 # 0xd5
+; CHECK-NEXT: .vbyte 2, 0 # 0x0
+; CHECK-NEXT: .csect .rodata.str4.4L..magic32[RO],2
+; CHECK-NEXT: .align 2
+; CHECK-NEXT: .vbyte 4, 464 # 0x1d0
+; CHECK-NEXT: .vbyte 4, 472 # 0x1d8
+; CHECK-NEXT: .vbyte 4, 413 # 0x19d
+; CHECK-NEXT: .vbyte 4, 0 # 0x0
+; CHECK-NEXT: .csect .rodata.str1.1L..strA[RO],2
+; CHECK-NEXT: .byte 'h,'e,'l,'l,'o,' ,'w,'o,'r,'l,'d,'!,0012,0000
+; CHECK-NEXT: .csect .rodata.str1.1L...str[RO],2
+; CHECK-NEXT: .byte 'a,'b,'c,'d,'e,'f,'g,'h,0000
; CHECKOBJ: 00000010 <.rodata.str2.2>:
; CHECKOBJ-NEXT: 10: 01 08 01 10
Index: llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
@@ -1,10 +1,10 @@
; This file tests the codegen of mergeable const in AIX assembly.
; This file also tests mergeable const in XCOFF object file generation.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s |\
; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < %s |\
; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
@@ -24,72 +24,132 @@
ret i32 0
}
-;CHECK: .csect .rodata[RO],4
+;CHECK: .csect .text[PR],2
-;CHECK-NEXT: .align 4
-;CHECK-NEXT: L..__const.main.cnst32:
-;CHECK32-NEXT: .vbyte 4, 1073741824
-;CHECK32-NEXT: .vbyte 4, 50
-;CHECK64-NEXT: .vbyte 8, 4611686018427387954
-;CHECK-NEXT: .vbyte 4, 0 # 0x0
+;CHECK: L..__const.main.cnst32[RO],4
+;CHECK-NEXT: .align 4
+;CHECK32-NEXT: .vbyte 4, 1073741824
+;CHECK32-NEXT: .vbyte 4, 50
+;CHECK64-NEXT: .vbyte 8, 4611686018427387954
+;CHECK-NEXT: .vbyte 4, 0 # 0x0
;CHECK-NEXT: .space 4
-;CHECK32-NEXT: .vbyte 4, 0
-;CHECK32-NEXT: .vbyte 4, 0
-;CHECK64-NEXT: .vbyte 8, 0
-;CHECK-NEXT: .vbyte 4, 0 # 0x0
+;CHECK32-NEXT: .vbyte 4, 0
+;CHECK32-NEXT: .vbyte 4, 0
+;CHECK64-NEXT: .vbyte 8, 0
+;CHECK-NEXT: .vbyte 4, 0 # 0x0
;CHECK-NEXT: .space 4
+;CHECK-NEXT: L..__const.main.cnst16[RO],3
;CHECK-NEXT: .align 3
-;CHECK-NEXT: L..__const.main.cnst16:
-;CHECK32-NEXT: .vbyte 4, 1073741824
-;CHECK32-NEXT: .vbyte 4, 22
-;CHECK64-NEXT: .vbyte 8, 4611686018427387926
-;CHECK-NEXT: .vbyte 4, 0 # 0x0
+;CHECK32-NEXT: .vbyte 4, 1073741824
+;CHECK32-NEXT: .vbyte 4, 22
+;CHECK64-NEXT: .vbyte 8, 4611686018427387926
+;CHECK-NEXT: .vbyte 4, 0 # 0x0
;CHECK-NEXT: .space 4
-;CHECK-NEXT: .align 3
-;CHECK-NEXT: L..__const.main.cnst8:
-;CHECK-NEXT: .vbyte 4, 1073741832 # 0x40000008
-;CHECK-NEXT: .vbyte 4, 0 # 0x0
+;CHECK-NEXT: L..__const.main.cnst8[RO],3
+;CHECK-NEXT: .align 3
+;CHECK-NEXT: .vbyte 4, 1073741832 # 0x40000008
+;CHECK-NEXT: .vbyte 4, 0 # 0x0
-;CHECK-NEXT: .align 3
-;CHECK-NEXT: L..__const.main.cnst4:
-;CHECK-NEXT: .vbyte 2, 16392 # 0x4008
-;CHECK-NEXT: .byte 0 # 0x0
-;CHECK-NEXT: .space 1
+;CHECK-NEXT: L..__const.main.cnst4[RO],3
+;CHECK-NEXT: .align 3
+;CHECK-NEXT: .vbyte 2, 16392 # 0x4008
+;CHECK-NEXT: .byte 0 # 0x0
+;CHECK-NEXT: .space 1
;CHECKOBJ: 00000000 <.text>:
;CHECKOBJ-NEXT: 0: 38 60 00 00 li 3, 0
;CHECKOBJ-NEXT: 4: 4e 80 00 20 blr
;CHECKOBJ-NEXT: ...{{[[:space:]] *}}
-;CHECKOBJ-NEXT: 00000010 <.rodata>:
+;CHECKOBJ-NEXT: 00000010 <L..__const.main.cnst32>:
;CHECKOBJ-NEXT: 10: 40 00 00 00
;CHECKOBJ-NEXT: 14: 00 00 00 32
;CHECKOBJ-NEXT: ...{{[[:space:]] *}}
-;CHECKOBJ-SAME: 30: 40 00 00 00
+;CHECKOBJ-NEXT: 00000030 <L..__const.main.cnst16>:
+;CHECKOBJ-NEXT: 30: 40 00 00 00
;CHECKOBJ-NEXT: 34: 00 00 00 16
;CHECKOBJ-NEXT: ...{{[[:space:]] *}}
-;CHECKOBJ-SAME: 40: 40 00 00 08
+;CHECKOBJ-NEXT: 00000040 <L..__const.main.cnst8>:
+;CHECKOBJ-NEXT: 40: 40 00 00 08
;CHECKOBJ-NEXT: 44: 00 00 00 00
+
+;CHECKOBJ: 00000048 <L..__const.main.cnst4>:
;CHECKOBJ-NEXT: 48: 40 08 00 00
+;CHECKSYM: Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: L..__const.main.cnst32
+;CHECKSYM-NEXT: Value (RelocatableAddress): 0x10
+;CHECKSYM-NEXT: Section: .text
+;CHECKSYM-NEXT: Type: 0x0
+;CHECKSYM-NEXT: StorageClass: C_HIDEXT (0x6B)
+;CHECKSYM-NEXT: NumberOfAuxEntries: 1
+;CHECKSYM-NEXT: CSECT Auxiliary Entry {
+;CHECKSYM-NEXT: Index: [[#Index+1]]
+;CHECKSYM-NEXT: SectionLen: 32
+;CHECKSYM-NEXT: ParameterHashIndex: 0x0
+;CHECKSYM-NEXT: TypeChkSectNum: 0x0
+;CHECKSYM-NEXT: SymbolAlignmentLog2: 4
+;CHECKSYM-NEXT: SymbolType: XTY_SD (0x1)
+;CHECKSYM-NEXT: StorageMappingClass: XMC_RO (0x1)
+;CHECKSYM-NEXT: StabInfoIndex: 0x0
+;CHECKSYM-NEXT: StabSectNum: 0x0
+;CHECKSYM-NEXT: }
+;CHECKSYM-NEXT: }
+
+;CHECKSYM: Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: L..__const.main.cnst16
+;CHECKSYM-NEXT: Value (RelocatableAddress): 0x30
+;CHECKSYM-NEXT: Section: .text
+;CHECKSYM-NEXT: Type: 0x0
+;CHECKSYM-NEXT: StorageClass: C_HIDEXT (0x6B)
+;CHECKSYM-NEXT: NumberOfAuxEntries: 1
+;CHECKSYM-NEXT: CSECT Auxiliary Entry {
+;CHECKSYM-NEXT: Index: [[#Index+1]]
+;CHECKSYM-NEXT: SectionLen: 16
+;CHECKSYM-NEXT: ParameterHashIndex: 0x0
+;CHECKSYM-NEXT: TypeChkSectNum: 0x0
+;CHECKSYM-NEXT: SymbolAlignmentLog2: 3
+;CHECKSYM-NEXT: SymbolType: XTY_SD (0x1)
+;CHECKSYM-NEXT: StorageMappingClass: XMC_RO (0x1)
+;CHECKSYM-NEXT: StabInfoIndex: 0x0
+;CHECKSYM-NEXT: StabSectNum: 0x0
+;CHECKSYM-NEXT: }
+;CHECKSYM-NEXT: }
-;CHECKSYM: Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: .rodata
-;CHECKSYM-NEXT: Value (RelocatableAddress): 0x10
-;CHECKSYM-NEXT: Section: .text
-;CHECKSYM-NEXT: Type: 0x0
-;CHECKSYM-NEXT: StorageClass: C_HIDEXT (0x6B)
-;CHECKSYM-NEXT: NumberOfAuxEntries: 1
-;CHECKSYM-NEXT: CSECT Auxiliary Entry {
-;CHECKSYM-NEXT: Index: [[#Index+1]]
-;CHECKSYM-NEXT: SectionLen: 60
-;CHECKSYM-NEXT: ParameterHashIndex: 0x0
-;CHECKSYM-NEXT: TypeChkSectNum: 0x0
-;CHECKSYM-NEXT: SymbolAlignmentLog2: 4
-;CHECKSYM-NEXT: SymbolType: XTY_SD (0x1)
-;CHECKSYM-NEXT: StorageMappingClass: XMC_RO (0x1)
-;CHECKSYM-NEXT: StabInfoIndex: 0x0
-;CHECKSYM-NEXT: StabSectNum: 0x0
-;CHECKSYM-NEXT: }
-;CHECKSYM-NEXT: }
+;CHECKSYM: Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: L..__const.main.cnst8
+;CHECKSYM-NEXT: Value (RelocatableAddress): 0x40
+;CHECKSYM-NEXT: Section: .text
+;CHECKSYM-NEXT: Type: 0x0
+;CHECKSYM-NEXT: StorageClass: C_HIDEXT (0x6B)
+;CHECKSYM-NEXT: NumberOfAuxEntries: 1
+;CHECKSYM-NEXT: CSECT Auxiliary Entry {
+;CHECKSYM-NEXT: Index: [[#Index+1]]
+;CHECKSYM-NEXT: SectionLen: 8
+;CHECKSYM-NEXT: ParameterHashIndex: 0x0
+;CHECKSYM-NEXT: TypeChkSectNum: 0x0
+;CHECKSYM-NEXT: SymbolAlignmentLog2: 3
+;CHECKSYM-NEXT: SymbolType: XTY_SD (0x1)
+;CHECKSYM-NEXT: StorageMappingClass: XMC_RO (0x1)
+;CHECKSYM-NEXT: StabInfoIndex: 0x0
+;CHECKSYM-NEXT: StabSectNum: 0x0
+;CHECKSYM-NEXT: }
+;CHECKSYM-NEXT: }
+
+;CHECKSYM: Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: L..__const.main.cnst4
+;CHECKSYM-NEXT: Value (RelocatableAddress): 0x48
+;CHECKSYM-NEXT: Section: .text
+;CHECKSYM-NEXT: Type: 0x0
+;CHECKSYM-NEXT: StorageClass: C_HIDEXT (0x6B)
+;CHECKSYM-NEXT: NumberOfAuxEntries: 1
+;CHECKSYM-NEXT: CSECT Auxiliary Entry {
+;CHECKSYM-NEXT: Index: [[#Index+1]]
+;CHECKSYM-NEXT: SectionLen: 4
+;CHECKSYM-NEXT: ParameterHashIndex: 0x0
+;CHECKSYM-NEXT: TypeChkSectNum: 0x0
+;CHECKSYM-NEXT: SymbolAlignmentLog2: 3
+;CHECKSYM-NEXT: SymbolType: XTY_SD (0x1)
+;CHECKSYM-NEXT: StorageMappingClass: XMC_RO (0x1)
+;CHECKSYM-NEXT: StabInfoIndex: 0x0
+;CHECKSYM-NEXT: StabSectNum: 0x0
+;CHECKSYM-NEXT: }
+;CHECKSYM-NEXT: }
Index: llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
@@ -1,26 +1,27 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj \
+; RUN: -data-sections -o %t.o < %s
; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < %s | \
; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < %s | \
; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
Index: llvm/test/CodeGen/PowerPC/aix-space.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-space.ll
+++ llvm/test/CodeGen/PowerPC/aix-space.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
@a = common global double 0.000000e+00, align 8
Index: llvm/test/CodeGen/PowerPC/aix-return55.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-return55.ll
+++ llvm/test/CodeGen/PowerPC/aix-return55.ll
@@ -1,9 +1,9 @@
-; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s
-; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -mcpu=pwr4 -vecnvol -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mcpu=pwr4 -vecnvol -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -filetype=obj -o %t.o < %s
; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
; RUN: llvm-readobj -sections %t.o | FileCheck --check-prefix=CHECKSECT %s
-; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
+; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -vecnvol -filetype=obj < %s 2>&1 | \
; RUN: FileCheck --check-prefix=XCOFF64 %s
; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
@@ -22,7 +22,7 @@
;CHECKOBJ: 00000000 <.text>:
;CHECKOBJ-NEXT: 0: 38 60 00 37 li 3, 55
;CHECKOBJ-NEXT: 4: 4e 80 00 20 blr{{[[:space:]] *}}
-;CHECKOBJ-NEXT: 00000008 <.rodata.str1.1>:
+;CHECKOBJ-NEXT: 00000008 <.rodata.str1.1L..strA>:
;CHECKOBJ-NEXT: 8: 68 65 6c 6c xori 5, 3, 27756
;CHECKOBJ-NEXT: c: 6f 77 6f 72 xoris 23, 27, 28530
;CHECKOBJ-NEXT: 10: 0a 00 00 00 tdlti 0, 0{{[[:space:]] *}}
Index: llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
+++ llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
-; RUN: -data-sections=false < %s | FileCheck %s
+; RUN: -vecnvol -data-sections=false < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
-; RUN: -data-sections=false < %s | FileCheck --check-prefix=CHECK64 %s
+; RUN: -vecnvol -data-sections=false < %s | FileCheck --check-prefix=CHECK64 %s
@foo_ptr = global void (...)* @foo
declare void @foo(...)
Index: llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
+++ llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
@@ -1,35 +1,35 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=32SMALL-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=32LARGE-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=64SMALL-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=64LARGE-MIR %s
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=small < %s | FileCheck \
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -vecnvol -code-model=small < %s | FileCheck \
; RUN: --check-prefixes=32SMALL-ASM,SMALL-ASM %s
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=large < %s | FileCheck \
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -vecnvol -code-model=large < %s | FileCheck \
; RUN: --check-prefixes=32LARGE-ASM,LARGE-ASM %s
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=small < %s | FileCheck \
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -vecnvol -code-model=small < %s | FileCheck \
; RUN: --check-prefixes=64SMALL-ASM,SMALL-ASM %s
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=large < %s | FileCheck \
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -vecnvol -code-model=large < %s | FileCheck \
; RUN: --check-prefixes=64LARGE-ASM,LARGE-ASM %s
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -function-sections < %s | FileCheck \
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -vecnvol -function-sections < %s | FileCheck \
; RUN: --check-prefixes=FUNC-ASM,CHECK %s
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -function-sections < %s | FileCheck \
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -vecnvol -function-sections < %s | FileCheck \
; RUN: --check-prefixes=FUNC-ASM,CHECK %s
define i32 @jump_table(i32 %a) {
Index: llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
+++ llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
@@ -1,29 +1,29 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=32SMALL-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=32LARGE-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=64SMALL-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=64LARGE-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s
define float @test_float() {
Index: llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
+++ llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
@@ -1,29 +1,29 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=32SMALL-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=32LARGE-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=64SMALL-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
; RUN: --check-prefix=64LARGE-MIR %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s
define void @foo() {
Index: llvm/test/CodeGen/PowerPC/aix-internal.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-internal.ll
+++ llvm/test/CodeGen/PowerPC/aix-internal.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4 \
+; RUN: llc -mtriple powerpc-ibm-aix -vecnvol -verify-machineinstrs -mcpu=pwr4 \
; RUN: -filetype=obj -o %t.o < %s
; RUN: llvm-readobj --syms %t.o | FileCheck %s
-; RUN: not --crash llc -mtriple powerpc64-ibm-aix -verify-machineinstrs -mcpu=pwr4 \
+; RUN: not --crash llc -mtriple powerpc64-ibm-aix -vecnvol -verify-machineinstrs -mcpu=pwr4 \
; RUN: -filetype=obj -o %t.o < %s 2>&1 | FileCheck --check-prefix=64-CHECK %s
define internal i32 @foo() {
Index: llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
+++ llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
; RUN: llvm-readobj --symbols %t.o | FileCheck %s
define void @foo() {
Index: llvm/test/CodeGen/PowerPC/aix-func-align.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-func-align.ll
+++ llvm/test/CodeGen/PowerPC/aix-func-align.ll
@@ -1,9 +1,9 @@
; This test tries to verify if a csect containing code would have the correct alignment.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s
; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
Index: llvm/test/CodeGen/PowerPC/aix-default-vec-abi.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-default-vec-abi.ll
@@ -0,0 +1,22 @@
+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s
+
+define dso_local <4 x i32> @vec_callee(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7, <4 x i32> %vec8, <4 x i32> %vec9, <4 x i32> %vec10, <4 x i32> %vec11, <4 x i32> %vec12, <4 x i32> %vec13, <4 x i32> %vec14) {
+ entry:
+ %add = add <4 x i32> %vec1, %vec2
+ %add1 = add <4 x i32> %add, %vec3
+ %add2 = add <4 x i32> %add1, %vec4
+ %add3 = add <4 x i32> %add2, %vec5
+ %add4 = add <4 x i32> %add3, %vec6
+ %add5 = add <4 x i32> %add4, %vec7
+ %add6 = add <4 x i32> %add5, %vec8
+ %add7 = add <4 x i32> %add6, %vec9
+ %add8 = add <4 x i32> %add7, %vec10
+ %add9 = add <4 x i32> %add8, %vec11
+ %add10 = add <4 x i32> %add9, %vec12
+ %add11 = add <4 x i32> %add10, %vec13
+ %add12 = add <4 x i32> %add11, %vec14
+ ret <4 x i32> %add12
+}
+
+; CHECK: LLVM ERROR: the default Altivec AIX ABI is not yet supported.
Index: llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
+++ llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < \
; RUN: %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < \
; RUN: %s | FileCheck %s
@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }]
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6922,6 +6922,10 @@
const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);
const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
+ if (ValVT.isVector() &&
+ !State.getMachineFunction().getTarget().Options.AIXExtendedAltivecABI)
+ report_fatal_error("the default Altivec AIX ABI is not yet supported.");
+
assert((!ValVT.isInteger() ||
(ValVT.getFixedSizeInBits() <= RegVT.getFixedSizeInBits())) &&
"Integer argument exceeds register size: should have been legalized");
Index: llvm/lib/CodeGen/CommandFlags.cpp
===================================================================
--- llvm/lib/CodeGen/CommandFlags.cpp
+++ llvm/lib/CodeGen/CommandFlags.cpp
@@ -58,6 +58,7 @@
CGOPT(bool, EnableNoNaNsFPMath)
CGOPT(bool, EnableNoSignedZerosFPMath)
CGOPT(bool, EnableNoTrappingFPMath)
+CGOPT(bool, AIXExtendedAltivecABI)
CGOPT(DenormalMode::DenormalModeKind, DenormalFPMath)
CGOPT(DenormalMode::DenormalModeKind, DenormalFP32Math)
CGOPT(bool, EnableHonorSignDependentRoundingFPMath)
@@ -279,6 +280,11 @@
cl::init(false));
CGBINDOPT(DontPlaceZerosInBSS);
+ static cl::opt<bool> AIXExtendedAltivecABI(
+ "vecnvol", cl::desc("Enable the AIX Extended Altivec ABI."),
+ cl::init(false));
+ CGBINDOPT(AIXExtendedAltivecABI);
+
static cl::opt<bool> EnableGuaranteedTailCallOpt(
"tailcallopt",
cl::desc(
@@ -480,6 +486,7 @@
getEnableHonorSignDependentRoundingFPMath();
if (getFloatABIForCalls() != FloatABI::Default)
Options.FloatABIType = getFloatABIForCalls();
+ Options.AIXExtendedAltivecABI = getAIXExtendedAltivecABI();
Options.NoZerosInBSS = getDontPlaceZerosInBSS();
Options.GuaranteedTailCallOpt = getEnableGuaranteedTailCallOpt();
Options.StackAlignmentOverride = getOverrideStackAlignment();
Index: llvm/include/llvm/Target/TargetOptions.h
===================================================================
--- llvm/include/llvm/Target/TargetOptions.h
+++ llvm/include/llvm/Target/TargetOptions.h
@@ -118,6 +118,7 @@
TargetOptions()
: UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
NoTrappingFPMath(true), NoSignedZerosFPMath(false),
+ AIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
@@ -169,6 +170,12 @@
/// argument or result as insignificant.
unsigned NoSignedZerosFPMath : 1;
+ /// AIXExtendedAltivecABI - This flag returns true when -mvecnvol is
+ /// specified. The code generator is then able to use both volatile and
+ /// nonvolitle vector regisers. When false, the code generator only uses
+ /// volatile vector registers which is the default setting on AIX.
+ unsigned AIXExtendedAltivecABI : 1;
+
/// HonorSignDependentRoundingFPMath - This returns true when the
/// -enable-sign-dependent-rounding-fp-math is specified. If this returns
/// false (the default), the code generator is allowed to assume that the
Index: llvm/include/llvm/Target/TargetMachine.h
===================================================================
--- llvm/include/llvm/Target/TargetMachine.h
+++ llvm/include/llvm/Target/TargetMachine.h
@@ -243,6 +243,10 @@
Options.SupportsDebugEntryValues = Enable;
}
+ bool getAIXExtendedAltivecABI() const {
+ return Options.AIXExtendedAltivecABI;
+ }
+
bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }
/// Return true if unique basic block section names must be generated.
Index: llvm/include/llvm/CodeGen/CommandFlags.h
===================================================================
--- llvm/include/llvm/CodeGen/CommandFlags.h
+++ llvm/include/llvm/CodeGen/CommandFlags.h
@@ -75,6 +75,8 @@
bool getEnableGuaranteedTailCallOpt();
+bool getAIXExtendedAltivecABI();
+
bool getDisableTailCalls();
bool getStackSymbolOrdering();
Index: clang/test/CodeGen/altivec.c
===================================================================
--- clang/test/CodeGen/altivec.c
+++ clang/test/CodeGen/altivec.c
@@ -1,5 +1,17 @@
// RUN: %clang_cc1 -target-feature +altivec -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
-
+// RUN: %clang_cc1 -target-feature +altivec -mvecnvol -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -mvecnvol -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -mvecnvol -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -mvecnvol -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -mnovecnvol -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
+// RUN: not %clang_cc1 -target-feature +altivec -mnovecnvol -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR
+
+// RUN: %clang -S -emit-llvm -maltivec -mvecnvol -target powerpc-unknown-aix %s -o - | FileCheck %s
+// RUN: not %clang -S -emit-llvm -mnovecnvol -target powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER
+// RUN: not %clang -S -emit-llvm -mvecnvol -target powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER
+// RUN: %clang -S -emit-llvm -maltivec -mvecnvol -target powerpc64-unknown-aix %s -o - | FileCheck %s
+// RUN: not %clang -S -emit-llvm -mnovecnvol -target powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER
+// RUN: not %clang -S -emit-llvm -mvecnvol -target powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER
// Check initialization
vector int test0 = (vector int)(1); // CHECK: @test0 = global <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -38,3 +50,6 @@
vector float vf;
vf++; // CHECK: fadd <4 x float> {{.*}} <float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}>
}
+
+// AIX-ERROR: error: The default Altivec ABI on AIX is not yet supported, use '-mvecnvol' for the extended Altivec ABI
+// AIX-ATVER: error: '-mvecnvol' and '-mnovecnvol' require '-maltivec'
Index: clang/lib/Frontend/CompilerInvocation.cpp
===================================================================
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -1364,6 +1364,22 @@
!Args.hasArg(OPT_fvisibility)))
Opts.IgnoreXCOFFVisibility = 1;
+ if (Arg *A = Args.getLastArg(OPT_mnovecnvol, OPT_mvecnvol)) {
+ if (!T.isOSAIX())
+ Diags.Report(diag::err_drv_unsupported_opt_for_target)
+ << A->getSpelling() << T.str();
+
+ const Option &O = A->getOption();
+ if (O.matches(OPT_mnovecnvol))
+ Diags.Report(diag::err_aix_default_altivec_abi)
+ << A->getSpelling() << T.str();
+ else {
+ assert(O.matches(OPT_mvecnvol));
+ Opts.AIXExtendedAltivecABI = 1;
+ }
+ }
+
+
Opts.DependentLibraries = Args.getAllArgValues(OPT_dependent_lib);
Opts.LinkerOptions = Args.getAllArgValues(OPT_linker_option);
bool NeedLocTracking = false;
Index: clang/lib/Driver/ToolChains/Clang.cpp
===================================================================
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -4569,6 +4569,33 @@
}
}
+ if (Arg *A =
+ Args.getLastArg(options::OPT_mvecnvol, options::OPT_mnovecnvol)) {
+
+ if (!RawTriple.isOSAIX())
+ D.Diag(diag::err_drv_unsupported_opt_for_target)
+ << A->getSpelling() << RawTriple.str();
+
+ bool haveMaltivec = false;
+
+ for (const Arg *A : Args) {
+ auto optID = A->getOption().getID();
+ switch (optID) {
+ default:
+ break;
+ case options::OPT_maltivec:
+ haveMaltivec = true;
+ }
+ }
+
+ if (A->getOption().matches(options::OPT_mnovecnvol) && haveMaltivec)
+ D.Diag(diag::err_aix_default_altivec_abi);
+ else if (A->getOption().matches(options::OPT_mvecnvol) && haveMaltivec)
+ CmdArgs.push_back("-mvecnvol");
+ else
+ D.Diag(diag::err_aix_altivec);
+ }
+
if (Arg *A = Args.getLastArg(options::OPT_Wframe_larger_than_EQ)) {
StringRef v = A->getValue();
CmdArgs.push_back("-mllvm");
Index: clang/lib/CodeGen/BackendUtil.cpp
===================================================================
--- clang/lib/CodeGen/BackendUtil.cpp
+++ clang/lib/CodeGen/BackendUtil.cpp
@@ -529,6 +529,7 @@
Options.EmitAddrsig = CodeGenOpts.Addrsig;
Options.ForceDwarfFrameSection = CodeGenOpts.ForceDwarfFrameSection;
Options.EmitCallSiteInfo = CodeGenOpts.EmitCallSiteInfo;
+ Options.AIXExtendedAltivecABI = CodeGenOpts.AIXExtendedAltivecABI;
Options.ValueTrackingVariableLocations =
CodeGenOpts.ValueTrackingVariableLocations;
Options.XRayOmitFunctionIndex = CodeGenOpts.XRayOmitFunctionIndex;
Index: clang/include/clang/Driver/Options.td
===================================================================
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -2493,6 +2493,10 @@
def mno_pcrel: Flag<["-"], "mno-pcrel">, Group<m_ppc_Features_Group>;
def mspe : Flag<["-"], "mspe">, Group<m_ppc_Features_Group>;
def mno_spe : Flag<["-"], "mno-spe">, Group<m_ppc_Features_Group>;
+def mvecnvol : Flag<["-"], "mvecnvol">, Group<m_Group>, Flags<[CC1Option]>,
+ HelpText<"Enable the extended Altivec ABI on AIX (AIX only). Uses volatile and nonvolatile vector registers">;
+def mnovecnvol : Flag<["-"], "mnovecnvol">, Group<m_Group>, Flags<[CC1Option]>,
+ HelpText<"Enable the default Altivec ABI on AIX (AIX only)">;
def mvsx : Flag<["-"], "mvsx">, Group<m_ppc_Features_Group>;
def mno_vsx : Flag<["-"], "mno-vsx">, Group<m_ppc_Features_Group>;
def msecure_plt : Flag<["-"], "msecure-plt">, Group<m_ppc_Features_Group>;
Index: clang/include/clang/Basic/DiagnosticDriverKinds.td
===================================================================
--- clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -524,4 +524,9 @@
def err_drv_invalid_sve_vector_bits : Error<
"'-msve-vector-bits' is not supported without SVE enabled">;
+
+def err_aix_default_altivec_abi : Error<
+ "The default Altivec ABI on AIX is not yet supported, use '-mvecnvol' for the extended Altivec ABI">;
+
+def err_aix_altivec : Error<"'-mvecnvol' and '-mnovecnvol' require '-maltivec'">;
}
Index: clang/include/clang/Basic/CodeGenOptions.def
===================================================================
--- clang/include/clang/Basic/CodeGenOptions.def
+++ clang/include/clang/Basic/CodeGenOptions.def
@@ -49,6 +49,7 @@
CODEGENOPT(UniqueBasicBlockSectionNames, 1, 1) ///< Set for -funique-basic-block-section-names,
///< Produce unique section names with
///< basic block sections.
+CODEGENOPT(AIXExtendedAltivecABI, 1, 0) ///< Set for -mvecnvol. Enables the extended Altivec ABI on AIX.
ENUM_CODEGENOPT(FramePointer, FramePointerKind, 2, FramePointerKind::None) /// frame-pointer: all,non-leaf,none
CODEGENOPT(DisableFree , 1, 0) ///< Don't free memory.
Index: clang/docs/ClangCommandLineReference.rst
===================================================================
--- clang/docs/ClangCommandLineReference.rst
+++ clang/docs/ClangCommandLineReference.rst
@@ -2865,6 +2865,10 @@
.. option:: -municode<arg>
+Only supported On AIX. Specify usage of volatile and nonvolatile vector registers, the extended vector ABI on AIX. Defaults to '-mnovecnvol' when Altivec is enabled.
+
+.. option:: -mvecnvol, -mnovecnvol
+
.. option:: -mvx, -mno-vx
.. option:: -mwarn-nonportable-cfstrings, -mno-warn-nonportable-cfstrings
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