uweigand added a comment.

In D87279#2334510 <https://reviews.llvm.org/D87279#2334510>, @jonpa wrote:

> The problem seems to be with a tied earlyclobber operand:
>
>   asm("" : "+&r"(a));
>
> Per the comment in InlineAsm::ConstraintInfo::Parse(), only output can be 
> earlyclobber.
>
> I am not sure if the earlyclobber ('&') should with this patch be removed 
> from the added use of the register, or if this has to for some reason really 
> be tied to the def?

So we have a read/write tied earlyclobber operand that is also tied to a phyreg 
via an asm register declaration?   That means that: the physreg is used as 
input, it is also used as output, and it is written to before all inputs are 
read (i.e. no *other* input may share the same register, even if it would 
otherwise hold the same value).

I believe there is no way to represent the effect of a read/write tied 
earlyclobber in any other way.  E.g. trying to use separate inputs/outputs (one 
with "=&r", one with "r") does not work since the earlyclobber on the output 
would prevent the same register to be used for the input, but it *has* to be 
the same register ...

On on other hand, in this special case the original problem cannot actually 
occur, because there cannot be any other input using the same physreg (that's 
what the earlyclobber ensures), so maybe be just don't do that transformation 
if an earlyclobber is present?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87279/new/

https://reviews.llvm.org/D87279

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