Author: Evandro Menezes Date: 2020-10-05T19:28:31-05:00 New Revision: a48d480e1f7ebc5d5f93507fe1f519496621e259
URL: https://github.com/llvm/llvm-project/commit/a48d480e1f7ebc5d5f93507fe1f519496621e259 DIFF: https://github.com/llvm/llvm-project/commit/a48d480e1f7ebc5d5f93507fe1f519496621e259.diff LOG: [RISCV] Fix broken test Fix test for the SiFive E76 core. This patch fixes the issue introduced by the commit 5d6d8a2769. Added: Modified: clang/test/Driver/riscv-cpus.c llvm/include/llvm/Support/RISCVTargetParser.def Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 2bd0b26f3caf..d551529f7827 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -31,9 +31,9 @@ // mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 | FileCheck -check-prefix=MCPU-SIFIVE-E76 %s // MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76" -// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E76: "-target-feature" "+c" -// MCPU-SIFIVE-E76: "-target-abi" "lp64d" +// MCPU-SIFIVE-E76: "-target-abi" "ilp32" // mcpu with mabi option // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s diff --git a/llvm/include/llvm/Support/RISCVTargetParser.def b/llvm/include/llvm/Support/RISCVTargetParser.def index a63874fa5dd0..53eebcf328d3 100644 --- a/llvm/include/llvm/Support/RISCVTargetParser.def +++ b/llvm/include/llvm/Support/RISCVTargetParser.def @@ -7,8 +7,8 @@ PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""}) PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""}) PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""}) PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""}) -PROC(BULLET_RV32, {"sifive-7-rv32"}, FK_NONE, {""}) -PROC(BULLET_RV64, {"sifive-7-rv64"}, FK_64BIT, {""}) +PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""}) +PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""}) PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"}) PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"}) _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
