[PATCH] D88265: Fix comma with half vectors.

[Alexandre Rames via Phabricator via cfe-commits]

arames created this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
arames requested review of this revision.

The current half vector was enforcing an assert expecting
 "(LHS is half vector) == (RHS is half vector)"
for comma.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88265

Files:
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Sema/fp16vec-sema.c


Index: clang/test/Sema/fp16vec-sema.c
===================================================================
--- clang/test/Sema/fp16vec-sema.c
+++ clang/test/Sema/fp16vec-sema.c
@@ -26,6 +26,7 @@
   sv0 = hv0 > hv1;
   sv0 = hv0 <= hv1;
   sv0 = hv0 >= hv1;
+  hv0, 1; // expected-warning 2 {{expression result unused}}
   sv0 = hv0 || hv1; // expected-error{{logical expression with vector types 
'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
   sv0 = hv0 && hv1; // expected-error{{logical expression with vector types 
'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
 
Index: clang/lib/Sema/SemaExpr.cpp
===================================================================
--- clang/lib/Sema/SemaExpr.cpp
+++ clang/lib/Sema/SemaExpr.cpp
@@ -13933,9 +13933,10 @@
   // float vectors and truncating the result back to half vector. For now, we 
do
   // this only when HalfArgsAndReturn is set (that is, when the target is arm 
or
   // arm64).
-  assert(isVector(RHS.get()->getType(), Context.HalfTy) ==
-         isVector(LHS.get()->getType(), Context.HalfTy) &&
-         "both sides are half vectors or neither sides are");
+  assert(Opc == BO_Comma ||
+         isVector(RHS.get()->getType(), Context.HalfTy) ==
+                 isVector(LHS.get()->getType(), Context.HalfTy) &&
+             "both sides are half vectors or neither sides are");
   ConvertHalfVec =
       needsConversionOfHalfVec(ConvertHalfVec, Context, LHS.get(), RHS.get());
 



Index: clang/test/Sema/fp16vec-sema.c
===================================================================
--- clang/test/Sema/fp16vec-sema.c
+++ clang/test/Sema/fp16vec-sema.c
@@ -26,6 +26,7 @@
   sv0 = hv0 > hv1;
   sv0 = hv0 <= hv1;
   sv0 = hv0 >= hv1;
+  hv0, 1; // expected-warning 2 {{expression result unused}}
   sv0 = hv0 || hv1; // expected-error{{logical expression with vector types 'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
   sv0 = hv0 && hv1; // expected-error{{logical expression with vector types 'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
 
Index: clang/lib/Sema/SemaExpr.cpp
===================================================================
--- clang/lib/Sema/SemaExpr.cpp
+++ clang/lib/Sema/SemaExpr.cpp
@@ -13933,9 +13933,10 @@
   // float vectors and truncating the result back to half vector. For now, we do
   // this only when HalfArgsAndReturn is set (that is, when the target is arm or
   // arm64).
-  assert(isVector(RHS.get()->getType(), Context.HalfTy) ==
-         isVector(LHS.get()->getType(), Context.HalfTy) &&
-         "both sides are half vectors or neither sides are");
+  assert(Opc == BO_Comma ||
+         isVector(RHS.get()->getType(), Context.HalfTy) ==
+                 isVector(LHS.get()->getType(), Context.HalfTy) &&
+             "both sides are half vectors or neither sides are");
   ConvertHalfVec =
       needsConversionOfHalfVec(ConvertHalfVec, Context, LHS.get(), RHS.get());
 

_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits