[PATCH] D88009: [AArch64] Fix return type of Neon scalar comparison intrinsics

David Spickett via Phabricator via cfe-commits Mon, 21 Sep 2020 03:07:47 -0700

DavidSpickett created this revision.
Herald added subscribers: cfe-commits, danielkiss, kristof.beyls.
Herald added a project: clang.
DavidSpickett requested review of this revision.


The following should have unsigned return types
but were signed:
vceqd_s64 vceqzd_s64 vcged_s64 vcgezd_s64
vcgtd_s64 vcgtzd_s64 vcled_s64 vclezd_s64
vcltd_s64 vcltzd_s64 vtstd_s64

See https://developer.arm.com/documentation/ihi0073/latest


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88009

Files:
  clang/include/clang/Basic/arm_neon.td
  clang/test/CodeGen/aarch64-neon-intrinsics.c

Index: clang/test/CodeGen/aarch64-neon-intrinsics.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-intrinsics.c
+++ clang/test/CodeGen/aarch64-neon-intrinsics.c
@@ -13746,8 +13746,8 @@
 // CHECK:   [[TMP0:%.*]] = icmp eq i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
-int64_t test_vceqd_s64(int64_t a, int64_t b) {
-  return (int64_t)vceqd_s64(a, b);
+uint64_t test_vceqd_s64(int64_t a, int64_t b) {
+  return (uint64_t)vceqd_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vceqd_u64(
@@ -13762,8 +13762,8 @@
 // CHECK:   [[TMP0:%.*]] = icmp eq i64 %a, 0
 // CHECK:   [[VCEQZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQZ_I]]
-int64_t test_vceqzd_s64(int64_t a) {
-  return (int64_t)vceqzd_s64(a);
+uint64_t test_vceqzd_s64(int64_t a) {
+  return (uint64_t)vceqzd_s64(a);
 }
 
 // CHECK-LABEL: @test_vceqzd_u64(
@@ -13778,8 +13778,8 @@
 // CHECK:   [[TMP0:%.*]] = icmp sge i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
-int64_t test_vcged_s64(int64_t a, int64_t b) {
-  return (int64_t)vcged_s64(a, b);
+uint64_t test_vcged_s64(int64_t a, int64_t b) {
+  return (uint64_t)vcged_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vcged_u64(
@@ -13794,16 +13794,16 @@
 // CHECK:   [[TMP0:%.*]] = icmp sge i64 %a, 0
 // CHECK:   [[VCGEZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCGEZ_I]]
-int64_t test_vcgezd_s64(int64_t a) {
-  return (int64_t)vcgezd_s64(a);
+uint64_t test_vcgezd_s64(int64_t a) {
+  return (uint64_t)vcgezd_s64(a);
 }
 
 // CHECK-LABEL: @test_vcgtd_s64(
 // CHECK:   [[TMP0:%.*]] = icmp sgt i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
-int64_t test_vcgtd_s64(int64_t a, int64_t b) {
-  return (int64_t)vcgtd_s64(a, b);
+uint64_t test_vcgtd_s64(int64_t a, int64_t b) {
+  return (uint64_t)vcgtd_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vcgtd_u64(
@@ -13818,16 +13818,16 @@
 // CHECK:   [[TMP0:%.*]] = icmp sgt i64 %a, 0
 // CHECK:   [[VCGTZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCGTZ_I]]
-int64_t test_vcgtzd_s64(int64_t a) {
-  return (int64_t)vcgtzd_s64(a);
+uint64_t test_vcgtzd_s64(int64_t a) {
+  return (uint64_t)vcgtzd_s64(a);
 }
 
 // CHECK-LABEL: @test_vcled_s64(
 // CHECK:   [[TMP0:%.*]] = icmp sle i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
-int64_t test_vcled_s64(int64_t a, int64_t b) {
-  return (int64_t)vcled_s64(a, b);
+uint64_t test_vcled_s64(int64_t a, int64_t b) {
+  return (uint64_t)vcled_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vcled_u64(
@@ -13842,16 +13842,16 @@
 // CHECK:   [[TMP0:%.*]] = icmp sle i64 %a, 0
 // CHECK:   [[VCLEZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCLEZ_I]]
-int64_t test_vclezd_s64(int64_t a) {
-  return (int64_t)vclezd_s64(a);
+uint64_t test_vclezd_s64(int64_t a) {
+  return (uint64_t)vclezd_s64(a);
 }
 
 // CHECK-LABEL: @test_vcltd_s64(
 // CHECK:   [[TMP0:%.*]] = icmp slt i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
-int64_t test_vcltd_s64(int64_t a, int64_t b) {
-  return (int64_t)vcltd_s64(a, b);
+uint64_t test_vcltd_s64(int64_t a, int64_t b) {
+  return (uint64_t)vcltd_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vcltd_u64(
@@ -13866,8 +13866,8 @@
 // CHECK:   [[TMP0:%.*]] = icmp slt i64 %a, 0
 // CHECK:   [[VCLTZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCLTZ_I]]
-int64_t test_vcltzd_s64(int64_t a) {
-  return (int64_t)vcltzd_s64(a);
+uint64_t test_vcltzd_s64(int64_t a) {
+  return (uint64_t)vcltzd_s64(a);
 }
 
 // CHECK-LABEL: @test_vtstd_s64(
@@ -13875,8 +13875,8 @@
 // CHECK:   [[TMP1:%.*]] = icmp ne i64 [[TMP0]], 0
 // CHECK:   [[VTSTD_I:%.*]] = sext i1 [[TMP1]] to i64
 // CHECK:   ret i64 [[VTSTD_I]]
-int64_t test_vtstd_s64(int64_t a, int64_t b) {
-  return (int64_t)vtstd_s64(a, b);
+uint64_t test_vtstd_s64(int64_t a, int64_t b) {
+  return (uint64_t)vtstd_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vtstd_u64(
Index: clang/include/clang/Basic/arm_neon.td
===================================================================
--- clang/include/clang/Basic/arm_neon.td
+++ clang/include/clang/Basic/arm_neon.td
@@ -1419,19 +1419,19 @@
 
 ////////////////////////////////////////////////////////////////////////////////
 // Scalar Integer Comparison
-def SCALAR_CMEQ : SInst<"vceq", "111", "SlSUl">;
-def SCALAR_CMEQZ : SInst<"vceqz", "11", "SlSUl">;
-def SCALAR_CMGE : SInst<"vcge", "111", "Sl">;
-def SCALAR_CMGEZ : SInst<"vcgez", "11", "Sl">;
-def SCALAR_CMHS : SInst<"vcge", "111", "SUl">;
-def SCALAR_CMLE : SInst<"vcle", "111", "SlSUl">;
-def SCALAR_CMLEZ : SInst<"vclez", "11", "Sl">;
-def SCALAR_CMLT : SInst<"vclt", "111", "SlSUl">;
-def SCALAR_CMLTZ : SInst<"vcltz", "11", "Sl">;
-def SCALAR_CMGT : SInst<"vcgt", "111", "Sl">;
-def SCALAR_CMGTZ : SInst<"vcgtz", "11", "Sl">;
-def SCALAR_CMHI : SInst<"vcgt", "111", "SUl">;
-def SCALAR_CMTST : SInst<"vtst", "111", "SlSUl">;
+def SCALAR_CMEQ : SInst<"vceq", "(U1)11", "SlSUl">;
+def SCALAR_CMEQZ : SInst<"vceqz", "(U1)1", "SlSUl">;
+def SCALAR_CMGE : SInst<"vcge", "(U1)11", "Sl">;
+def SCALAR_CMGEZ : SInst<"vcgez", "(U1)1", "Sl">;
+def SCALAR_CMHS : SInst<"vcge", "(U1)11", "SUl">;
+def SCALAR_CMLE : SInst<"vcle", "(U1)11", "SlSUl">;
+def SCALAR_CMLEZ : SInst<"vclez", "(U1)1", "Sl">;
+def SCALAR_CMLT : SInst<"vclt", "(U1)11", "SlSUl">;
+def SCALAR_CMLTZ : SInst<"vcltz", "(U1)1", "Sl">;
+def SCALAR_CMGT : SInst<"vcgt", "(U1)11", "Sl">;
+def SCALAR_CMGTZ : SInst<"vcgtz", "(U1)1", "Sl">;
+def SCALAR_CMHI : SInst<"vcgt", "(U1)11", "SUl">;
+def SCALAR_CMTST : SInst<"vtst", "(U1)11", "SlSUl">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Scalar Floating-point Comparison

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[PATCH] D88009: [AArch64] Fix return type of Neon scalar comparison intrinsics

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