FreddyYe created this revision.
FreddyYe added reviewers: craig.topper, pengfei, LuoYuanke.
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FreddyYe requested review of this revision.
Support -march=sapphirerapids for x86.
Compare with Icelake Server, it includes 14 more new features. They are
amxtile, amxint8, amxbf16, avx512bf16, avx512vp2intersect, cldemote,
enqcmd, movdir64b, movdiri, prwrite, serialize, shstk, tsxldtrk, waitpkg.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D86503
Files:
clang/lib/Basic/Targets/X86.cpp
clang/test/CodeGen/attr-target-mv.c
clang/test/CodeGen/target-builtin-noerror.c
clang/test/Driver/x86-march.c
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/predefined-arch-macros.c
compiler-rt/lib/builtins/cpu_model.c
llvm/include/llvm/Support/X86TargetParser.def
llvm/include/llvm/Support/X86TargetParser.h
llvm/lib/Support/Host.cpp
llvm/lib/Support/X86TargetParser.cpp
llvm/lib/Target/X86/X86.td
llvm/test/CodeGen/X86/cpus-intel.ll
Index: llvm/test/CodeGen/X86/cpus-intel.ll
===================================================================
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -40,6 +40,7 @@
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=atom 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
Index: llvm/lib/Target/X86/X86.td
===================================================================
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -741,6 +741,25 @@
list<SubtargetFeature> TGLFeatures =
!listconcat(ICLFeatures, TGLAdditionalFeatures );
+ //Sapphirerapids
+ list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE,
+ FeatureAMXINT8,
+ FeatureAMXBF16,
+ FeatureBF16,
+ FeatureSERIALIZE,
+ FeatureCLDEMOTE,
+ FeatureWAITPKG,
+ FeaturePTWRITE,
+ FeatureTSXLDTRK,
+ FeatureENQCMD,
+ FeatureSHSTK,
+ FeatureVP2INTERSECT,
+ FeatureMOVDIRI,
+ FeatureMOVDIR64B];
+ list<SubtargetFeature> SPRTuning = ICXTuning;
+ list<SubtargetFeature> SPRFeatures =
+ !listconcat(ICXFeatures, SPRAdditionalFeatures);
+
// Atom
list<SubtargetFeature> AtomFeatures = [FeatureX87,
FeatureCMPXCHG8B,
@@ -1237,6 +1256,8 @@
ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
def : ProcModel<"tigerlake", SkylakeServerModel,
ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
+def : ProcModel<"sapphirerapids", SkylakeServerModel,
+ ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
// AMD CPUs.
Index: llvm/lib/Support/X86TargetParser.cpp
===================================================================
--- llvm/lib/Support/X86TargetParser.cpp
+++ llvm/lib/Support/X86TargetParser.cpp
@@ -195,6 +195,11 @@
static constexpr FeatureBitset FeaturesTigerlake =
FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
FeatureMOVDIRI | FeatureSHSTK;
+static constexpr FeatureBitset FeaturesSapphireRapids =
+ FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
+ FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE | FeatureENQCMD |
+ FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE |
+ FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG;
// Intel Atom processors.
// Bonnell has feature parity with Core2 and adds MOVBE.
@@ -342,6 +347,8 @@
{ {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
// Tigerlake microarchitecture based processors.
{ {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
+ // Sapphire Rapids microarchitecture based processors.
+ { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
// Knights Landing processor.
{ {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
// Knights Mill processor.
Index: llvm/lib/Support/Host.cpp
===================================================================
--- llvm/lib/Support/Host.cpp
+++ llvm/lib/Support/Host.cpp
@@ -730,6 +730,13 @@
*Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
break;
+ // Sapphire Rapids:
+ case 0x8f:
+ CPU = "sapphirerapids";
+ *Type = X86::INTEL_COREI7;
+ *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
+ break;
+
case 0x1c: // Most 45 nm Intel Atom processors
case 0x26: // 45 nm Atom Lincroft
case 0x27: // 32 nm Atom Medfield
Index: llvm/include/llvm/Support/X86TargetParser.h
===================================================================
--- llvm/include/llvm/Support/X86TargetParser.h
+++ llvm/include/llvm/Support/X86TargetParser.h
@@ -100,6 +100,7 @@
CK_IcelakeClient,
CK_IcelakeServer,
CK_Tigerlake,
+ CK_SapphireRapids,
CK_KNL,
CK_KNM,
CK_Lakemont,
Index: llvm/include/llvm/Support/X86TargetParser.def
===================================================================
--- llvm/include/llvm/Support/X86TargetParser.def
+++ llvm/include/llvm/Support/X86TargetParser.def
@@ -84,6 +84,7 @@
X86_CPU_SUBTYPE(INTEL_COREI7_CASCADELAKE, "cascadelake")
X86_CPU_SUBTYPE(INTEL_COREI7_TIGERLAKE, "tigerlake")
X86_CPU_SUBTYPE(INTEL_COREI7_COOPERLAKE, "cooperlake")
+X86_CPU_SUBTYPE(INTEL_COREI7_SAPPHIRERAPIDS, "sapphirerapids")
#undef X86_CPU_SUBTYPE
Index: compiler-rt/lib/builtins/cpu_model.c
===================================================================
--- compiler-rt/lib/builtins/cpu_model.c
+++ compiler-rt/lib/builtins/cpu_model.c
@@ -84,6 +84,7 @@
INTEL_COREI7_CASCADELAKE,
INTEL_COREI7_TIGERLAKE,
INTEL_COREI7_COOPERLAKE,
+ INTEL_COREI7_SAPPHIRERAPIDS,
CPU_SUBTYPE_MAX
};
@@ -407,6 +408,13 @@
*Subtype = INTEL_COREI7_ICELAKE_SERVER;
break;
+ // Sapphire Rapids:
+ case 0x8f:
+ CPU = "sapphirerapids";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_SAPPHIRERAPIDS;
+ break;
+
case 0x1c: // Most 45 nm Intel Atom processors
case 0x26: // 45 nm Atom Lincroft
case 0x27: // 32 nm Atom Medfield
Index: clang/test/Preprocessor/predefined-arch-macros.c
===================================================================
--- clang/test/Preprocessor/predefined-arch-macros.c
+++ clang/test/Preprocessor/predefined-arch-macros.c
@@ -1629,6 +1629,145 @@
// CHECK_TGL_M64: #define __x86_64 1
// CHECK_TGL_M64: #define __x86_64__ 1
+// RUN: %clang -march=sapphirerapids -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPR_M32
+// CHECK_SPR_M32: #define __AES__ 1
+// CHECK_SPR_M32: #define __AMXBF16__ 1
+// CHECK_SPR_M32: #define __AMXINT8__ 1
+// CHECK_SPR_M32: #define __AMXTILE__ 1
+// CHECK_SPR_M32: #define __AVX2__ 1
+// CHECK_SPR_M32: #define __AVX512BF16__ 1
+// CHECK_SPR_M32: #define __AVX512BITALG__ 1
+// CHECK_SPR_M32: #define __AVX512BW__ 1
+// CHECK_SPR_M32: #define __AVX512CD__ 1
+// CHECK_SPR_M32: #define __AVX512DQ__ 1
+// CHECK_SPR_M32: #define __AVX512F__ 1
+// CHECK_SPR_M32: #define __AVX512IFMA__ 1
+// CHECK_SPR_M32: #define __AVX512VBMI2__ 1
+// CHECK_SPR_M32: #define __AVX512VBMI__ 1
+// CHECK_SPR_M32: #define __AVX512VL__ 1
+// CHECK_SPR_M32: #define __AVX512VNNI__ 1
+// CHECK_SPR_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_SPR_M32: #define __AVX__ 1
+// CHECK_SPR_M32: #define __BMI2__ 1
+// CHECK_SPR_M32: #define __BMI__ 1
+// CHECK_SPR_M32: #define __CLDEMOTE__ 1
+// CHECK_SPR_M32: #define __CLFLUSHOPT__ 1
+// CHECK_SPR_M32: #define __CLWB__ 1
+// CHECK_SPR_M32: #define __ENQCMD__ 1
+// CHECK_SPR_M32: #define __F16C__ 1
+// CHECK_SPR_M32: #define __FMA__ 1
+// CHECK_SPR_M32: #define __GFNI__ 1
+// CHECK_SPR_M32: #define __INVPCID__ 1
+// CHECK_SPR_M32: #define __LZCNT__ 1
+// CHECK_SPR_M32: #define __MMX__ 1
+// CHECK_SPR_M32: #define __MOVBE__ 1
+// CHECK_SPR_M32: #define __PCLMUL__ 1
+// CHECK_SPR_M32: #define __PCONFIG__ 1
+// CHECK_SPR_M32: #define __PKU__ 1
+// CHECK_SPR_M32: #define __POPCNT__ 1
+// CHECK_SPR_M32: #define __PRFCHW__ 1
+// CHECK_SPR_M32: #define __PTWRITE__ 1
+// CHECK_SPR_M32: #define __RDPID__ 1
+// CHECK_SPR_M32: #define __RDRND__ 1
+// CHECK_SPR_M32: #define __RDSEED__ 1
+// CHECK_SPR_M32: #define __SERIALIZE__ 1
+// CHECK_SPR_M32: #define __SGX__ 1
+// CHECK_SPR_M32: #define __SHA__ 1
+// CHECK_SPR_M32: #define __SHSTK__ 1
+// CHECK_SPR_M32: #define __SSE2__ 1
+// CHECK_SPR_M32: #define __SSE3__ 1
+// CHECK_SPR_M32: #define __SSE4_1__ 1
+// CHECK_SPR_M32: #define __SSE4_2__ 1
+// CHECK_SPR_M32: #define __SSE__ 1
+// CHECK_SPR_M32: #define __SSSE3__ 1
+// CHECK_SPR_M32: #define __TSXLDTRK__ 1
+// CHECK_SPR_M32: #define __VAES__ 1
+// CHECK_SPR_M32: #define __VPCLMULQDQ__ 1
+// CHECK_SPR_M32: #define __WAITPKG__ 1
+// CHECK_SPR_M32: #define __WBNOINVD__ 1
+// CHECK_SPR_M32: #define __XSAVEC__ 1
+// CHECK_SPR_M32: #define __XSAVEOPT__ 1
+// CHECK_SPR_M32: #define __XSAVES__ 1
+// CHECK_SPR_M32: #define __XSAVE__ 1
+// CHECK_SPR_M32: #define __corei7 1
+// CHECK_SPR_M32: #define __corei7__ 1
+// CHECK_SPR_M32: #define __i386 1
+// CHECK_SPR_M32: #define __i386__ 1
+// CHECK_SPR_M32: #define __tune_corei7__ 1
+// CHECK_SPR_M32: #define i386 1
+
+// RUN: %clang -march=sapphirerapids -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPR_M64
+// CHECK_SPR_M64: #define __AES__ 1
+// CHECK_SPR_M64: #define __AMXBF16__ 1
+// CHECK_SPR_M64: #define __AMXINT8__ 1
+// CHECK_SPR_M64: #define __AMXTILE__ 1
+// CHECK_SPR_M64: #define __AVX2__ 1
+// CHECK_SPR_M64: #define __AVX512BF16__ 1
+// CHECK_SPR_M64: #define __AVX512BITALG__ 1
+// CHECK_SPR_M64: #define __AVX512BW__ 1
+// CHECK_SPR_M64: #define __AVX512CD__ 1
+// CHECK_SPR_M64: #define __AVX512DQ__ 1
+// CHECK_SPR_M64: #define __AVX512F__ 1
+// CHECK_SPR_M64: #define __AVX512IFMA__ 1
+// CHECK_SPR_M64: #define __AVX512VBMI2__ 1
+// CHECK_SPR_M64: #define __AVX512VBMI__ 1
+// CHECK_SPR_M64: #define __AVX512VL__ 1
+// CHECK_SPR_M64: #define __AVX512VNNI__ 1
+// CHECK_SPR_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_SPR_M64: #define __AVX__ 1
+// CHECK_SPR_M64: #define __BMI2__ 1
+// CHECK_SPR_M64: #define __BMI__ 1
+// CHECK_SPR_M64: #define __CLDEMOTE__ 1
+// CHECK_SPR_M64: #define __CLFLUSHOPT__ 1
+// CHECK_SPR_M64: #define __CLWB__ 1
+// CHECK_SPR_M64: #define __ENQCMD__ 1
+// CHECK_SPR_M64: #define __F16C__ 1
+// CHECK_SPR_M64: #define __FMA__ 1
+// CHECK_SPR_M64: #define __GFNI__ 1
+// CHECK_SPR_M64: #define __INVPCID__ 1
+// CHECK_SPR_M64: #define __LZCNT__ 1
+// CHECK_SPR_M64: #define __MMX__ 1
+// CHECK_SPR_M64: #define __MOVBE__ 1
+// CHECK_SPR_M64: #define __PCLMUL__ 1
+// CHECK_SPR_M64: #define __PCONFIG__ 1
+// CHECK_SPR_M64: #define __PKU__ 1
+// CHECK_SPR_M64: #define __POPCNT__ 1
+// CHECK_SPR_M64: #define __PRFCHW__ 1
+// CHECK_SPR_M64: #define __PTWRITE__ 1
+// CHECK_SPR_M64: #define __RDPID__ 1
+// CHECK_SPR_M64: #define __RDRND__ 1
+// CHECK_SPR_M64: #define __RDSEED__ 1
+// CHECK_SPR_M64: #define __SERIALIZE__ 1
+// CHECK_SPR_M64: #define __SGX__ 1
+// CHECK_SPR_M64: #define __SHA__ 1
+// CHECK_SPR_M64: #define __SHSTK__ 1
+// CHECK_SPR_M64: #define __SSE2__ 1
+// CHECK_SPR_M64: #define __SSE3__ 1
+// CHECK_SPR_M64: #define __SSE4_1__ 1
+// CHECK_SPR_M64: #define __SSE4_2__ 1
+// CHECK_SPR_M64: #define __SSE__ 1
+// CHECK_SPR_M64: #define __SSSE3__ 1
+// CHECK_SPR_M64: #define __TSXLDTRK__ 1
+// CHECK_SPR_M64: #define __VAES__ 1
+// CHECK_SPR_M64: #define __VPCLMULQDQ__ 1
+// CHECK_SPR_M64: #define __WAITPKG__ 1
+// CHECK_SPR_M64: #define __WBNOINVD__ 1
+// CHECK_SPR_M64: #define __XSAVEC__ 1
+// CHECK_SPR_M64: #define __XSAVEOPT__ 1
+// CHECK_SPR_M64: #define __XSAVES__ 1
+// CHECK_SPR_M64: #define __XSAVE__ 1
+// CHECK_SPR_M64: #define __amd64 1
+// CHECK_SPR_M64: #define __amd64__ 1
+// CHECK_SPR_M64: #define __corei7 1
+// CHECK_SPR_M64: #define __corei7__ 1
+// CHECK_SPR_M64: #define __tune_corei7__ 1
+// CHECK_SPR_M64: #define __x86_64 1
+// CHECK_SPR_M64: #define __x86_64__ 1
+
// RUN: %clang -march=atom -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATOM_M32
Index: clang/test/Misc/target-invalid-cpu-note.c
===================================================================
--- clang/test/Misc/target-invalid-cpu-note.c
+++ clang/test/Misc/target-invalid-cpu-note.c
@@ -21,7 +21,7 @@
// X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
// X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
// X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
-// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, knl, knm, lakemont, k6, k6-2, k6-3,
+// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, knl, knm, lakemont, k6, k6-2, k6-3,
// X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
// X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
// X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2,
@@ -33,7 +33,7 @@
// X86_64-SAME: atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere,
// X86_64-SAME: sandybridge, corei7-avx, ivybridge, core-avx-i, haswell,
// X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake,
-// X86_64-SAME: icelake-client, icelake-server, tigerlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
+// X86_64-SAME: icelake-client, icelake-server, tigerlake, sapphirerapids, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
// X86_64-SAME: athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1,
// X86_64-SAME: btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, x86-64
Index: clang/test/Driver/x86-march.c
===================================================================
--- clang/test/Driver/x86-march.c
+++ clang/test/Driver/x86-march.c
@@ -104,6 +104,10 @@
// RUN: | FileCheck %s -check-prefix=tremont
// tremont: "-target-cpu" "tremont"
//
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=sapphirerapids 2>&1 \
+// RUN: | FileCheck %s -check-prefix=sapphirerapids
+// sapphirerapids: "-target-cpu" "sapphirerapids"
+//
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=k8 2>&1 \
// RUN: | FileCheck %s -check-prefix=k8
// k8: "-target-cpu" "k8"
Index: clang/test/CodeGen/target-builtin-noerror.c
===================================================================
--- clang/test/CodeGen/target-builtin-noerror.c
+++ clang/test/CodeGen/target-builtin-noerror.c
@@ -122,6 +122,7 @@
(void)__builtin_cpu_is("skylake-avx512");
(void)__builtin_cpu_is("slm");
(void)__builtin_cpu_is("tigerlake");
+ (void)__builtin_cpu_is("sapphirerapids");
(void)__builtin_cpu_is("tremont");
(void)__builtin_cpu_is("westmere");
(void)__builtin_cpu_is("znver1");
Index: clang/test/CodeGen/attr-target-mv.c
===================================================================
--- clang/test/CodeGen/attr-target-mv.c
+++ clang/test/CodeGen/attr-target-mv.c
@@ -11,6 +11,7 @@
int __attribute__((target("arch=icelake-server"))) foo(void) {return 7;}
int __attribute__((target("arch=cooperlake"))) foo(void) {return 8;}
int __attribute__((target("arch=tigerlake"))) foo(void) {return 9;}
+int __attribute__((target("arch=sapphirerapids"))) foo(void) {return 10;}
int __attribute__((target("default"))) foo(void) { return 2; }
int bar() {
@@ -91,6 +92,8 @@
// LINUX: ret i32 8
// LINUX: define i32 @foo.arch_tigerlake()
// LINUX: ret i32 9
+// LINUX: define i32 @foo.arch_sapphirerapids()
+// LINUX: ret i32 10
// LINUX: define i32 @foo()
// LINUX: ret i32 2
// LINUX: define i32 @bar()
Index: clang/lib/Basic/Targets/X86.cpp
===================================================================
--- clang/lib/Basic/Targets/X86.cpp
+++ clang/lib/Basic/Targets/X86.cpp
@@ -459,6 +459,7 @@
case CK_IcelakeClient:
case CK_IcelakeServer:
case CK_Tigerlake:
+ case CK_SapphireRapids:
// FIXME: Historically, we defined this legacy name, it would be nice to
// remove it at some point. We've never exposed fine-grained names for
// recent primary x86 CPUs, and we should keep it that way.
@@ -1269,6 +1270,7 @@
case CK_Cooperlake:
case CK_Cannonlake:
case CK_Tigerlake:
+ case CK_SapphireRapids:
case CK_IcelakeClient:
case CK_IcelakeServer:
case CK_KNL:
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