amyk added inline comments.
================
Comment at: llvm/test/CodeGen/PowerPC/p10-vector-divide.ll:59
+
+define <4 x i32> @test_vdivesw(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vdivesw:
----------------
NeHuang wrote:
> nit: do we also need `_intrinsic` in the name as the test cases for the
> vector multiply high intrinsics.
I am thinking that it may be OK to leave the vector divide extended tests
without the `_intrinsic` suffix.
The reason why I added `_intrinsic` to vector multiply high is because the
vector multiply high instructions can be produced in two ways:
- by the `mulhs` node (which is present in the test, I have named them
`test_vmulh...`)
- by the `@llvm.ppc.altivec.vmulh[s|u][w|d]` intrinsic (these tests have the
`_intrinsic` suffix)
So far for the vector divide extended, we produce the instructions only if we
have the intrinsic.
However I do not feel too strongly either way on this so if there is a
preference to add `_intrinsic` to these tests, I can definitely do that.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82609/new/
https://reviews.llvm.org/D82609
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