[PATCH] D85599: [Clang] Consider __builtin_trap() and __builtin_debugtrap() as terminator

[Zhang Kang via Phabricator via cfe-commits]

ZhangKang updated this revision to Diff 284424.
ZhangKang added a comment.
Herald added a subscriber: hiraditya.

Remoeve isTerminator for TRAP instruction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85599/new/

https://reviews.llvm.org/D85599

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins.ll


Index: llvm/test/CodeGen/PowerPC/builtins.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+
+define void @test_builtin_trap() {
+; CHECK-LABEL: test_builtin_trap:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    stw 3, -4(1)
+; CHECK-NEXT:    trap
+; CHECK-NEXT:    lwz 3, -4(1)
+; CHECK-NEXT:    stw 3, -8(1)
+; CHECK-NEXT:    blr
+entry:
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  store volatile i32 0, i32* %i, align 4
+  call void @llvm.trap()
+  %0 = load volatile i32, i32* %i, align 4
+  store volatile i32 %0, i32* %j, align 4
+  ret void
+}
+
+declare void @llvm.trap()
+
+define void @test_builtin_debugtrap() {
+; CHECK-LABEL: test_builtin_debugtrap:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    stw 3, -4(1)
+; CHECK-NEXT:    trap
+; CHECK-NEXT:    lwz 3, -4(1)
+; CHECK-NEXT:    stw 3, -8(1)
+; CHECK-NEXT:    blr
+entry:
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  store volatile i32 0, i32* %i, align 4
+  call void @llvm.debugtrap()
+  %0 = load volatile i32, i32* %i, align 4
+  store volatile i32 %0, i32* %j, align 4
+  ret void
+}
+
+declare void @llvm.debugtrap()
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2060,7 +2060,7 @@
                           "stwat $rS, $rA, $FC", IIC_LdStStore>,
             Requires<[IsISA3_0]>;
 
-let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isBarrier = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),



Index: llvm/test/CodeGen/PowerPC/builtins.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+
+define void @test_builtin_trap() {
+; CHECK-LABEL: test_builtin_trap:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    stw 3, -4(1)
+; CHECK-NEXT:    trap
+; CHECK-NEXT:    lwz 3, -4(1)
+; CHECK-NEXT:    stw 3, -8(1)
+; CHECK-NEXT:    blr
+entry:
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  store volatile i32 0, i32* %i, align 4
+  call void @llvm.trap()
+  %0 = load volatile i32, i32* %i, align 4
+  store volatile i32 %0, i32* %j, align 4
+  ret void
+}
+
+declare void @llvm.trap()
+
+define void @test_builtin_debugtrap() {
+; CHECK-LABEL: test_builtin_debugtrap:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    stw 3, -4(1)
+; CHECK-NEXT:    trap
+; CHECK-NEXT:    lwz 3, -4(1)
+; CHECK-NEXT:    stw 3, -8(1)
+; CHECK-NEXT:    blr
+entry:
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  store volatile i32 0, i32* %i, align 4
+  call void @llvm.debugtrap()
+  %0 = load volatile i32, i32* %i, align 4
+  store volatile i32 %0, i32* %j, align 4
+  ret void
+}
+
+declare void @llvm.debugtrap()
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2060,7 +2060,7 @@
                           "stwat $rS, $rA, $FC", IIC_LdStStore>,
             Requires<[IsISA3_0]>;
 
-let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isBarrier = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),

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