HsiangKai updated this revision to Diff 267447.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80802/new/
https://reviews.llvm.org/D80802
Files:
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Driver/riscv-arch.c
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/test/MC/RISCV/rvv/convert.s
llvm/test/MC/RISCV/rvv/ext.s
llvm/test/MC/RISCV/rvv/fothers.s
llvm/test/MC/RISCV/rvv/invalid.s
llvm/test/MC/RISCV/rvv/load.s
llvm/test/MC/RISCV/rvv/mask.s
llvm/test/MC/RISCV/rvv/snippet.s
llvm/test/MC/RISCV/rvv/store.s
llvm/test/MC/RISCV/rvv/vsetvl.s
Index: llvm/test/MC/RISCV/rvv/vsetvl.s
===================================================================
--- llvm/test/MC/RISCV/rvv/vsetvl.s
+++ llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -8,12 +8,72 @@
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vsetvli a2, a0, e32,m1
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 <unknown>
+
+vsetvli a2, a0, e32,m2
+# CHECK-INST: vsetvli a2, a0, e32,m2
+# CHECK-ENCODING: [0x57,0x76,0x95,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 00 <unknown>
+
vsetvli a2, a0, e32,m4
# CHECK-INST: vsetvli a2, a0, e32,m4
# CHECK-ENCODING: [0x57,0x76,0xa5,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 a5 00 <unknown>
+vsetvli a2, a0, e32,m8
+# CHECK-INST: vsetvli a2, a0, e32,m8
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 00 <unknown>
+
+vsetvli a2, a0, e32,mf2
+# CHECK-INST: vsetvli a2, a0, e32,mf2
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 02 <unknown>
+
+vsetvli a2, a0, e32,mf4
+# CHECK-INST: vsetvli a2, a0, e32,mf4
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 a5 02 <unknown>
+
+vsetvli a2, a0, e32,mf8
+# CHECK-INST: vsetvli a2, a0, e32,mf8
+# CHECK-ENCODING: [0x57,0x76,0x95,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 02 <unknown>
+
+vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 0c <unknown>
+
+vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 08 <unknown>
+
+vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-ENCODING: [0x57,0x76,0x85,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 04 <unknown>
+
+vsetvli a2, a0, e32,m1,tu,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 <unknown>
+
vsetvl a2, a0, a1
# CHECK-INST: vsetvl a2, a0, a1
# CHECK-ENCODING: [0x57,0x76,0xb5,0x80]
Index: llvm/test/MC/RISCV/rvv/store.s
===================================================================
--- llvm/test/MC/RISCV/rvv/store.s
+++ llvm/test/MC/RISCV/rvv/store.s
@@ -8,200 +8,296 @@
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-vsb.v v24, (a0), v0.t
-# CHECK-INST: vsb.v v24, (a0), v0.t
+vse8.v v24, (a0), v0.t
+# CHECK-INST: vse8.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 05 00 <unknown>
-vsb.v v24, (a0)
-# CHECK-INST: vsb.v v24, (a0)
+vse8.v v24, (a0)
+# CHECK-INST: vse8.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 05 02 <unknown>
-vsh.v v24, (a0), v0.t
-# CHECK-INST: vsh.v v24, (a0), v0.t
+vse16.v v24, (a0), v0.t
+# CHECK-INST: vse16.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x5c,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 05 00 <unknown>
-vsh.v v24, (a0)
-# CHECK-INST: vsh.v v24, (a0)
+vse16.v v24, (a0)
+# CHECK-INST: vse16.v v24, (a0)
# CHECK-ENCODING: [0x27,0x5c,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 05 02 <unknown>
-vsw.v v24, (a0), v0.t
-# CHECK-INST: vsw.v v24, (a0), v0.t
+vse32.v v24, (a0), v0.t
+# CHECK-INST: vse32.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x6c,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 05 00 <unknown>
-vsw.v v24, (a0)
-# CHECK-INST: vsw.v v24, (a0)
+vse32.v v24, (a0)
+# CHECK-INST: vse32.v v24, (a0)
# CHECK-ENCODING: [0x27,0x6c,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 05 02 <unknown>
-vse.v v24, (a0), v0.t
-# CHECK-INST: vse.v v24, (a0), v0.t
+vse64.v v24, (a0), v0.t
+# CHECK-INST: vse64.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x7c,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 05 00 <unknown>
-vse.v v24, (a0)
-# CHECK-INST: vse.v v24, (a0)
+vse64.v v24, (a0)
+# CHECK-INST: vse64.v v24, (a0)
# CHECK-ENCODING: [0x27,0x7c,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 05 02 <unknown>
-vssb.v v24, (a0), a1, v0.t
-# CHECK-INST: vssb.v v24, (a0), a1, v0.t
+vse128.v v24, (a0), v0.t
+# CHECK-INST: vse128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 05 10 <unknown>
+
+vse128.v v24, (a0)
+# CHECK-INST: vse128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 05 12 <unknown>
+
+vse256.v v24, (a0), v0.t
+# CHECK-INST: vse256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 05 10 <unknown>
+
+vse256.v v24, (a0)
+# CHECK-INST: vse256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 05 12 <unknown>
+
+vse512.v v24, (a0), v0.t
+# CHECK-INST: vse512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 05 10 <unknown>
+
+vse512.v v24, (a0)
+# CHECK-INST: vse512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 05 12 <unknown>
+
+vse1024.v v24, (a0), v0.t
+# CHECK-INST: vse1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 05 10 <unknown>
+
+vse1024.v v24, (a0)
+# CHECK-INST: vse1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 05 12 <unknown>
+
+vsse8.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse8.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c b5 08 <unknown>
-vssb.v v24, (a0), a1
-# CHECK-INST: vssb.v v24, (a0), a1
+vsse8.v v24, (a0), a1
+# CHECK-INST: vsse8.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c b5 0a <unknown>
-vssh.v v24, (a0), a1, v0.t
-# CHECK-INST: vssh.v v24, (a0), a1, v0.t
+vsse16.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse16.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c b5 08 <unknown>
-vssh.v v24, (a0), a1
-# CHECK-INST: vssh.v v24, (a0), a1
+vsse16.v v24, (a0), a1
+# CHECK-INST: vsse16.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c b5 0a <unknown>
-vssw.v v24, (a0), a1, v0.t
-# CHECK-INST: vssw.v v24, (a0), a1, v0.t
+vsse32.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse32.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c b5 08 <unknown>
-vssw.v v24, (a0), a1
-# CHECK-INST: vssw.v v24, (a0), a1
+vsse32.v v24, (a0), a1
+# CHECK-INST: vsse32.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c b5 0a <unknown>
-vsse.v v24, (a0), a1, v0.t
-# CHECK-INST: vsse.v v24, (a0), a1, v0.t
+vsse64.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse64.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c b5 08 <unknown>
-vsse.v v24, (a0), a1
-# CHECK-INST: vsse.v v24, (a0), a1
+vsse64.v v24, (a0), a1
+# CHECK-INST: vsse64.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c b5 0a <unknown>
-vsxb.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxb.v v24, (a0), v4, v0.t
+vsse128.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c b5 18 <unknown>
+
+vsse128.v v24, (a0), a1
+# CHECK-INST: vsse128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c b5 1a <unknown>
+
+vsse256.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c b5 18 <unknown>
+
+vsse256.v v24, (a0), a1
+# CHECK-INST: vsse256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c b5 1a <unknown>
+
+vsse512.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c b5 18 <unknown>
+
+vsse512.v v24, (a0), a1
+# CHECK-INST: vsse512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c b5 1a <unknown>
+
+vsse1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c b5 18 <unknown>
+
+vsse1024.v v24, (a0), a1
+# CHECK-INST: vsse1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c b5 1a <unknown>
+
+vsxei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 45 0c <unknown>
-vsxb.v v24, (a0), v4
-# CHECK-INST: vsxb.v v24, (a0), v4
+vsxei8.v v24, (a0), v4
+# CHECK-INST: vsxei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 45 0e <unknown>
-vsxh.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxh.v v24, (a0), v4, v0.t
+vsxei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 45 0c <unknown>
-vsxh.v v24, (a0), v4
-# CHECK-INST: vsxh.v v24, (a0), v4
+vsxei16.v v24, (a0), v4
+# CHECK-INST: vsxei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 45 0e <unknown>
-vsxw.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxw.v v24, (a0), v4, v0.t
+vsxei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 45 0c <unknown>
-vsxw.v v24, (a0), v4
-# CHECK-INST: vsxw.v v24, (a0), v4
+vsxei32.v v24, (a0), v4
+# CHECK-INST: vsxei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 45 0e <unknown>
-vsxe.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxe.v v24, (a0), v4, v0.t
+vsxei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 45 0c <unknown>
-vsxe.v v24, (a0), v4
-# CHECK-INST: vsxe.v v24, (a0), v4
+vsxei64.v v24, (a0), v4
+# CHECK-INST: vsxei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 45 0e <unknown>
-vsuxb.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxb.v v24, (a0), v4, v0.t
+vsxei128.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei128.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 45 1c <unknown>
-vsuxb.v v24, (a0), v4
-# CHECK-INST: vsuxb.v v24, (a0), v4
+vsxei128.v v24, (a0), v4
+# CHECK-INST: vsxei128.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x1e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 45 1e <unknown>
-vsuxh.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxh.v v24, (a0), v4, v0.t
+vsxei256.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei256.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 45 1c <unknown>
-vsuxh.v v24, (a0), v4
-# CHECK-INST: vsuxh.v v24, (a0), v4
+vsxei256.v v24, (a0), v4
+# CHECK-INST: vsxei256.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x1e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 45 1e <unknown>
-vsuxw.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxw.v v24, (a0), v4, v0.t
+vsxei512.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei512.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 45 1c <unknown>
-vsuxw.v v24, (a0), v4
-# CHECK-INST: vsuxw.v v24, (a0), v4
+vsxei512.v v24, (a0), v4
+# CHECK-INST: vsxei512.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x1e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 45 1e <unknown>
-vsuxe.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxe.v v24, (a0), v4, v0.t
+vsxei1024.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei1024.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 45 1c <unknown>
-vsuxe.v v24, (a0), v4
-# CHECK-INST: vsuxe.v v24, (a0), v4
+vsxei1024.v v24, (a0), v4
+# CHECK-INST: vsxei1024.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x1e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 45 1e <unknown>
vs1r.v v24, (a0)
# CHECK-INST: vs1r.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x85,0x02]
+# CHECK-ENCODING: [0x27,0x0c,0x85,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 7c 85 02 <unknown>
+# CHECK-UNKNOWN: 27 0c 85 02 <unknown>
Index: llvm/test/MC/RISCV/rvv/snippet.s
===================================================================
--- llvm/test/MC/RISCV/rvv/snippet.s
+++ llvm/test/MC/RISCV/rvv/snippet.s
@@ -7,8 +7,8 @@
loop:
vsetvli a3, a0, e16,m4 # vtype = 16-bit integer vectors
# CHECK-INST: d7 76 65 00 vsetvli a3, a0, e16,m4
- vlh.v v4, (a1) # Get 16b vector
-# CHECK-INST: 07 d2 05 12 vlh.v v4, (a1)
+ vle16.v v4, (a1) # Get 16b vector
+# CHECK-INST: 07 d2 05 02 vle16.v v4, (a1)
slli t1, a3, 1 # Multiply length by two bytes/element
# CHECK-INST: 13 93 16 00 slli t1, a3, 1
add a1, a1, t1 # Bump pointer
@@ -20,8 +20,8 @@
# CHECK-INST: 57 70 b5 00 vsetvli zero, a0, e32,m8
vsrl.vi v8, v8, 3
# CHECK-INST: 57 b4 81 a2 vsrl.vi v8, v8, 3
- vsw.v v8, (a2) # Store vector of 32b
-# CHECK-INST: 27 64 06 02 vsw.v v8, (a2)
+ vse32.v v8, (a2) # Store vector of 32b
+# CHECK-INST: 27 64 06 02 vse32.v v8, (a2)
slli t1, a3, 2 # Multiply length by four bytes/element
# CHECK-INST: 13 93 26 00 slli t1, a3, 2
add a2, a2, t1 # Bump pointer
Index: llvm/test/MC/RISCV/rvv/mask.s
===================================================================
--- llvm/test/MC/RISCV/rvv/mask.s
+++ llvm/test/MC/RISCV/rvv/mask.s
@@ -140,8 +140,8 @@
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 a4 08 52 <unknown>
-vmcpy.m v8, v4
-# CHECK-INST: vmcpy.m v8, v4
+vmmv.m v8, v4
+# CHECK-INST: vmmv.m v8, v4
# CHECK-ENCODING: [0x57,0x24,0x42,0x66]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 24 42 66 <unknown>
Index: llvm/test/MC/RISCV/rvv/load.s
===================================================================
--- llvm/test/MC/RISCV/rvv/load.s
+++ llvm/test/MC/RISCV/rvv/load.s
@@ -8,332 +8,392 @@
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-vlb.v v8, (a0), v0.t
-# CHECK-INST: vlb.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x10]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 10 <unknown>
-
-vlb.v v8, (a0)
-# CHECK-INST: vlb.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x12]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 12 <unknown>
-
-vlh.v v8, (a0), v0.t
-# CHECK-INST: vlh.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x10]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 10 <unknown>
-
-vlh.v v8, (a0)
-# CHECK-INST: vlh.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x12]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 12 <unknown>
-
-vlw.v v8, (a0), v0.t
-# CHECK-INST: vlw.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x10]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 10 <unknown>
-
-vlw.v v8, (a0)
-# CHECK-INST: vlw.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x12]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 12 <unknown>
-
-vlbu.v v8, (a0), v0.t
-# CHECK-INST: vlbu.v v8, (a0), v0.t
+vle8.v v8, (a0), v0.t
+# CHECK-INST: vle8.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 05 00 <unknown>
-vlbu.v v8, (a0)
-# CHECK-INST: vlbu.v v8, (a0)
+vle8.v v8, (a0)
+# CHECK-INST: vle8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 05 02 <unknown>
-vlhu.v v8, (a0), v0.t
-# CHECK-INST: vlhu.v v8, (a0), v0.t
+vle16.v v8, (a0), v0.t
+# CHECK-INST: vle16.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 05 00 <unknown>
-vlhu.v v8, (a0)
-# CHECK-INST: vlhu.v v8, (a0)
+vle16.v v8, (a0)
+# CHECK-INST: vle16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 05 02 <unknown>
-vlwu.v v8, (a0), v0.t
-# CHECK-INST: vlwu.v v8, (a0), v0.t
+vle32.v v8, (a0), v0.t
+# CHECK-INST: vle32.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 05 00 <unknown>
-vlwu.v v8, (a0)
-# CHECK-INST: vlwu.v v8, (a0)
+vle32.v v8, (a0)
+# CHECK-INST: vle32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 05 02 <unknown>
-vlbff.v v8, (a0), v0.t
-# CHECK-INST: vlbff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x11]
+vle64.v v8, (a0), v0.t
+# CHECK-INST: vle64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 11 <unknown>
+# CHECK-UNKNOWN: 07 74 05 00 <unknown>
-vlbff.v v8, (a0)
-# CHECK-INST: vlbff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x13]
+vle64.v v8, (a0)
+# CHECK-INST: vle64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 13 <unknown>
+# CHECK-UNKNOWN: 07 74 05 02 <unknown>
-vlhff.v v8, (a0), v0.t
-# CHECK-INST: vlhff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x11]
+vle128.v v8, (a0), v0.t
+# CHECK-INST: vle128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x10]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 11 <unknown>
+# CHECK-UNKNOWN: 07 04 05 10 <unknown>
-vlhff.v v8, (a0)
-# CHECK-INST: vlhff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x13]
+vle128.v v8, (a0)
+# CHECK-INST: vle128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x12]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 13 <unknown>
+# CHECK-UNKNOWN: 07 04 05 12 <unknown>
-vlwff.v v8, (a0), v0.t
-# CHECK-INST: vlwff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x11]
+vle256.v v8, (a0), v0.t
+# CHECK-INST: vle256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x10]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 11 <unknown>
+# CHECK-UNKNOWN: 07 54 05 10 <unknown>
-vlwff.v v8, (a0)
-# CHECK-INST: vlwff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x13]
+vle256.v v8, (a0)
+# CHECK-INST: vle256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x12]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 13 <unknown>
+# CHECK-UNKNOWN: 07 54 05 12 <unknown>
-vlbuff.v v8, (a0), v0.t
-# CHECK-INST: vlbuff.v v8, (a0), v0.t
+vle512.v v8, (a0), v0.t
+# CHECK-INST: vle512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 10 <unknown>
+
+vle512.v v8, (a0)
+# CHECK-INST: vle512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 12 <unknown>
+
+vle1024.v v8, (a0), v0.t
+# CHECK-INST: vle1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 10 <unknown>
+
+vle1024.v v8, (a0)
+# CHECK-INST: vle1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 12 <unknown>
+
+vle8ff.v v8, (a0), v0.t
+# CHECK-INST: vle8ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x01]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 05 01 <unknown>
-vlbuff.v v8, (a0)
-# CHECK-INST: vlbuff.v v8, (a0)
+vle8ff.v v8, (a0)
+# CHECK-INST: vle8ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x03]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 05 03 <unknown>
-vlhuff.v v8, (a0), v0.t
-# CHECK-INST: vlhuff.v v8, (a0), v0.t
+vle16ff.v v8, (a0), v0.t
+# CHECK-INST: vle16ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x01]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 05 01 <unknown>
-vlhuff.v v8, (a0)
-# CHECK-INST: vlhuff.v v8, (a0)
+vle16ff.v v8, (a0)
+# CHECK-INST: vle16ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x03]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 05 03 <unknown>
-vlwuff.v v8, (a0), v0.t
-# CHECK-INST: vlwuff.v v8, (a0), v0.t
+vle32ff.v v8, (a0), v0.t
+# CHECK-INST: vle32ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x01]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 05 01 <unknown>
-vlwuff.v v8, (a0)
-# CHECK-INST: vlwuff.v v8, (a0)
+vle32ff.v v8, (a0)
+# CHECK-INST: vle32ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x03]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 05 03 <unknown>
-vleff.v v8, (a0), v0.t
-# CHECK-INST: vleff.v v8, (a0), v0.t
+vle64ff.v v8, (a0), v0.t
+# CHECK-INST: vle64ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0x01]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 05 01 <unknown>
-vleff.v v8, (a0)
-# CHECK-INST: vleff.v v8, (a0)
+vle64ff.v v8, (a0)
+# CHECK-INST: vle64ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0x03]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 05 03 <unknown>
-vlsb.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsb.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x18]
+vle128ff.v v8, (a0), v0.t
+# CHECK-INST: vle128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x11]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 b5 18 <unknown>
+# CHECK-UNKNOWN: 07 04 05 11 <unknown>
-vlsb.v v8, (a0), a1
-# CHECK-INST: vlsb.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a]
+vle128ff.v v8, (a0)
+# CHECK-INST: vle128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x13]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 b5 1a <unknown>
+# CHECK-UNKNOWN: 07 04 05 13 <unknown>
-vlsh.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsh.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x18]
+vle256ff.v v8, (a0), v0.t
+# CHECK-INST: vle256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x11]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 b5 18 <unknown>
+# CHECK-UNKNOWN: 07 54 05 11 <unknown>
-vlsh.v v8, (a0), a1
-# CHECK-INST: vlsh.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a]
+vle256ff.v v8, (a0)
+# CHECK-INST: vle256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x13]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 b5 1a <unknown>
+# CHECK-UNKNOWN: 07 54 05 13 <unknown>
-vlsw.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsw.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x18]
+vle512ff.v v8, (a0), v0.t
+# CHECK-INST: vle512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x11]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 b5 18 <unknown>
+# CHECK-UNKNOWN: 07 64 05 11 <unknown>
-vlsw.v v8, (a0), a1
-# CHECK-INST: vlsw.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a]
+vle512ff.v v8, (a0)
+# CHECK-INST: vle512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x13]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 b5 1a <unknown>
+# CHECK-UNKNOWN: 07 64 05 13 <unknown>
+
+vle1024ff.v v8, (a0), v0.t
+# CHECK-INST: vle1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x11]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 11 <unknown>
+
+vle1024ff.v v8, (a0)
+# CHECK-INST: vle1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x13]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 13 <unknown>
-vlsbu.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsbu.v v8, (a0), a1, v0.t
+vlse8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse8.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x04,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 b5 08 <unknown>
-vlsbu.v v8, (a0), a1
-# CHECK-INST: vlsbu.v v8, (a0), a1
+vlse8.v v8, (a0), a1
+# CHECK-INST: vlse8.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x04,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 b5 0a <unknown>
-vlshu.v v8, (a0), a1, v0.t
-# CHECK-INST: vlshu.v v8, (a0), a1, v0.t
+vlse16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse16.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x54,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 b5 08 <unknown>
-vlshu.v v8, (a0), a1
-# CHECK-INST: vlshu.v v8, (a0), a1
+vlse16.v v8, (a0), a1
+# CHECK-INST: vlse16.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x54,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 b5 0a <unknown>
-vlswu.v v8, (a0), a1, v0.t
-# CHECK-INST: vlswu.v v8, (a0), a1, v0.t
+vlse32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse32.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x64,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 b5 08 <unknown>
-vlswu.v v8, (a0), a1
-# CHECK-INST: vlswu.v v8, (a0), a1
+vlse32.v v8, (a0), a1
+# CHECK-INST: vlse32.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x64,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 b5 0a <unknown>
-vlse.v v8, (a0), a1, v0.t
-# CHECK-INST: vlse.v v8, (a0), a1, v0.t
+vlse64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse64.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x74,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 b5 08 <unknown>
-vlse.v v8, (a0), a1
-# CHECK-INST: vlse.v v8, (a0), a1
+vlse64.v v8, (a0), a1
+# CHECK-INST: vlse64.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x74,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 b5 0a <unknown>
-vlxb.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxb.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x1c]
+vlse128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x18]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 45 1c <unknown>
+# CHECK-UNKNOWN: 07 04 b5 18 <unknown>
-vlxb.v v8, (a0), v4
-# CHECK-INST: vlxb.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x1e]
+vlse128.v v8, (a0), a1
+# CHECK-INST: vlse128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 45 1e <unknown>
+# CHECK-UNKNOWN: 07 04 b5 1a <unknown>
-vlxh.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxh.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x1c]
+vlse256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x18]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 45 1c <unknown>
+# CHECK-UNKNOWN: 07 54 b5 18 <unknown>
-vlxh.v v8, (a0), v4
-# CHECK-INST: vlxh.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x1e]
+vlse256.v v8, (a0), a1
+# CHECK-INST: vlse256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 45 1e <unknown>
+# CHECK-UNKNOWN: 07 54 b5 1a <unknown>
-vlxw.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxw.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x1c]
+vlse512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x18]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 45 1c <unknown>
+# CHECK-UNKNOWN: 07 64 b5 18 <unknown>
-vlxw.v v8, (a0), v4
-# CHECK-INST: vlxw.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x1e]
+vlse512.v v8, (a0), a1
+# CHECK-INST: vlse512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 45 1e <unknown>
+# CHECK-UNKNOWN: 07 64 b5 1a <unknown>
+
+vlse1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 b5 18 <unknown>
-vlxbu.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxbu.v v8, (a0), v4, v0.t
+vlse1024.v v8, (a0), a1
+# CHECK-INST: vlse1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 b5 1a <unknown>
+
+vlxei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 45 0c <unknown>
-vlxbu.v v8, (a0), v4
-# CHECK-INST: vlxbu.v v8, (a0), v4
+vlxei8.v v8, (a0), v4
+# CHECK-INST: vlxei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 45 0e <unknown>
-vlxhu.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxhu.v v8, (a0), v4, v0.t
+vlxei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 45 0c <unknown>
-vlxhu.v v8, (a0), v4
-# CHECK-INST: vlxhu.v v8, (a0), v4
+vlxei16.v v8, (a0), v4
+# CHECK-INST: vlxei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 45 0e <unknown>
-vlxwu.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxwu.v v8, (a0), v4, v0.t
+vlxei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 45 0c <unknown>
-vlxwu.v v8, (a0), v4
-# CHECK-INST: vlxwu.v v8, (a0), v4
+vlxei32.v v8, (a0), v4
+# CHECK-INST: vlxei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 45 0e <unknown>
-vlxe.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxe.v v8, (a0), v4, v0.t
+vlxei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 45 0c <unknown>
-vlxe.v v8, (a0), v4
-# CHECK-INST: vlxe.v v8, (a0), v4
+vlxei64.v v8, (a0), v4
+# CHECK-INST: vlxei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 45 0e <unknown>
+vlxei128.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei128.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 1c <unknown>
+
+vlxei128.v v8, (a0), v4
+# CHECK-INST: vlxei128.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 1e <unknown>
+
+vlxei256.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei256.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 1c <unknown>
+
+vlxei256.v v8, (a0), v4
+# CHECK-INST: vlxei256.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 1e <unknown>
+
+vlxei512.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei512.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 1c <unknown>
+
+vlxei512.v v8, (a0), v4
+# CHECK-INST: vlxei512.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 1e <unknown>
+
+vlxei1024.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei1024.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 1c <unknown>
+
+vlxei1024.v v8, (a0), v4
+# CHECK-INST: vlxei1024.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 1e <unknown>
+
vl1r.v v8, (a0)
# CHECK-INST: vl1r.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x85,0x02]
+# CHECK-ENCODING: [0x07,0x04,0x85,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 74 85 02 <unknown>
+# CHECK-UNKNOWN: 07 04 85 02 <unknown>
Index: llvm/test/MC/RISCV/rvv/invalid.s
===================================================================
--- llvm/test/MC/RISCV/rvv/invalid.s
+++ llvm/test/MC/RISCV/rvv/invalid.s
@@ -2,22 +2,34 @@
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
vsetvli a2, a0, e31
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vsetvli a2, a0, e32,m3
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vsetvli a2, a0, m1,e32
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vsetvli a2, a0, e32,m16
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vsetvli a2, a0, e2048,m8
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vsetvli a2, a0, e1,m8
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,tx
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,ta,mx
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,ma
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,mu
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vadd.vv v1, v3, v2, v4.t
# CHECK-ERROR: operand must be v0.t
Index: llvm/test/MC/RISCV/rvv/fothers.s
===================================================================
--- llvm/test/MC/RISCV/rvv/fothers.s
+++ llvm/test/MC/RISCV/rvv/fothers.s
@@ -10,30 +10,54 @@
vfsqrt.v v8, v4, v0.t
# CHECK-INST: vfsqrt.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x40,0x8c]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x4c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 8c <unknown>
+# CHECK-UNKNOWN: 57 14 40 4c <unknown>
vfsqrt.v v8, v4
# CHECK-INST: vfsqrt.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x40,0x8e]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x4e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 8e <unknown>
+# CHECK-UNKNOWN: 57 14 40 4e <unknown>
vfclass.v v8, v4, v0.t
# CHECK-INST: vfclass.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x48,0x8c]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x4c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 8c <unknown>
+# CHECK-UNKNOWN: 57 14 48 4c <unknown>
vfclass.v v8, v4
# CHECK-INST: vfclass.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x48,0x8e]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x4e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 8e <unknown>
+# CHECK-UNKNOWN: 57 14 48 4e <unknown>
vfmerge.vfm v8, v4, fa0, v0
# CHECK-INST: vfmerge.vfm v8, v4, fa0, v0
# CHECK-ENCODING: [0x57,0x54,0x45,0x5c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 54 45 5c <unknown>
+
+vfslide1up.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfslide1up.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 38 <unknown>
+
+vfslide1up.vf v8, v4, fa0
+# CHECK-INST: vfslide1up.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 3a <unknown>
+
+vfslide1down.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfslide1down.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 3c <unknown>
+
+vfslide1down.vf v8, v4, fa0
+# CHECK-INST: vfslide1down.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 3e <unknown>
Index: llvm/test/MC/RISCV/rvv/ext.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/ext.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vzext.vf2 v8, v4, v0.t
+# CHECK-INST: vzext.vf2 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 43 48 <unknown>
+
+vzext.vf2 v8, v4
+# CHECK-INST: vzext.vf2 v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 43 4a <unknown>
+
+vsext.vf2 v8, v4, v0.t
+# CHECK-INST: vsext.vf2 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 43 48 <unknown>
+
+vsext.vf2 v8, v4
+# CHECK-INST: vsext.vf2 v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 43 4a <unknown>
+
+vzext.vf4 v8, v4, v0.t
+# CHECK-INST: vzext.vf4 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x42,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 42 48 <unknown>
+
+vzext.vf4 v8, v4
+# CHECK-INST: vzext.vf4 v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x42,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 42 4a <unknown>
+
+vsext.vf4 v8, v4, v0.t
+# CHECK-INST: vsext.vf4 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x42,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 42 48 <unknown>
+
+vsext.vf4 v8, v4
+# CHECK-INST: vsext.vf4 v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x42,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 42 4a <unknown>
+
+vzext.vf8 v8, v4, v0.t
+# CHECK-INST: vzext.vf8 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x41,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 41 48 <unknown>
+
+vzext.vf8 v8, v4
+# CHECK-INST: vzext.vf8 v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x41,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 41 4a <unknown>
+
+vsext.vf8 v8, v4, v0.t
+# CHECK-INST: vsext.vf8 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x41,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 41 48 <unknown>
+
+vsext.vf8 v8, v4
+# CHECK-INST: vsext.vf8 v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x41,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 41 4a <unknown>
Index: llvm/test/MC/RISCV/rvv/convert.s
===================================================================
--- llvm/test/MC/RISCV/rvv/convert.s
+++ llvm/test/MC/RISCV/rvv/convert.s
@@ -10,180 +10,252 @@
vfcvt.xu.f.v v8, v4, v0.t
# CHECK-INST: vfcvt.xu.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x40,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 88 <unknown>
+# CHECK-UNKNOWN: 57 14 40 48 <unknown>
vfcvt.xu.f.v v8, v4
# CHECK-INST: vfcvt.xu.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x40,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 8a <unknown>
+# CHECK-UNKNOWN: 57 14 40 4a <unknown>
vfcvt.x.f.v v8, v4, v0.t
# CHECK-INST: vfcvt.x.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x40,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x40,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 40 88 <unknown>
+# CHECK-UNKNOWN: 57 94 40 48 <unknown>
vfcvt.x.f.v v8, v4
# CHECK-INST: vfcvt.x.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x40,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x40,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 40 8a <unknown>
+# CHECK-UNKNOWN: 57 94 40 4a <unknown>
vfcvt.f.xu.v v8, v4, v0.t
# CHECK-INST: vfcvt.f.xu.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x41,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x41,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 41 88 <unknown>
+# CHECK-UNKNOWN: 57 14 41 48 <unknown>
vfcvt.f.xu.v v8, v4
# CHECK-INST: vfcvt.f.xu.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x41,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x41,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 41 8a <unknown>
+# CHECK-UNKNOWN: 57 14 41 4a <unknown>
vfcvt.f.x.v v8, v4, v0.t
# CHECK-INST: vfcvt.f.x.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x41,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x41,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 41 88 <unknown>
+# CHECK-UNKNOWN: 57 94 41 48 <unknown>
vfcvt.f.x.v v8, v4
# CHECK-INST: vfcvt.f.x.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x41,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x41,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 41 8a <unknown>
+# CHECK-UNKNOWN: 57 94 41 4a <unknown>
+
+vfcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-INST: vfcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 43 48 <unknown>
+
+vfcvt.rtz.xu.f.v v8, v4
+# CHECK-INST: vfcvt.rtz.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 43 4a <unknown>
+
+vfcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-INST: vfcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 43 48 <unknown>
+
+vfcvt.rtz.x.f.v v8, v4
+# CHECK-INST: vfcvt.rtz.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 43 4a <unknown>
vfwcvt.xu.f.v v8, v4, v0.t
# CHECK-INST: vfwcvt.xu.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x44,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x44,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 44 88 <unknown>
+# CHECK-UNKNOWN: 57 14 44 48 <unknown>
vfwcvt.xu.f.v v8, v4
# CHECK-INST: vfwcvt.xu.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x44,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x44,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 44 8a <unknown>
+# CHECK-UNKNOWN: 57 14 44 4a <unknown>
vfwcvt.x.f.v v8, v4, v0.t
# CHECK-INST: vfwcvt.x.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x44,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x44,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 44 88 <unknown>
+# CHECK-UNKNOWN: 57 94 44 48 <unknown>
vfwcvt.x.f.v v8, v4
# CHECK-INST: vfwcvt.x.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x44,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x44,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 44 8a <unknown>
+# CHECK-UNKNOWN: 57 94 44 4a <unknown>
vfwcvt.f.xu.v v8, v4, v0.t
# CHECK-INST: vfwcvt.f.xu.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x45,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x45,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 45 88 <unknown>
+# CHECK-UNKNOWN: 57 14 45 48 <unknown>
vfwcvt.f.xu.v v8, v4
# CHECK-INST: vfwcvt.f.xu.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x45,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x45,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 45 8a <unknown>
+# CHECK-UNKNOWN: 57 14 45 4a <unknown>
vfwcvt.f.x.v v8, v4, v0.t
# CHECK-INST: vfwcvt.f.x.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x45,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x45,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 45 88 <unknown>
+# CHECK-UNKNOWN: 57 94 45 48 <unknown>
vfwcvt.f.x.v v8, v4
# CHECK-INST: vfwcvt.f.x.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x45,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x45,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 45 8a <unknown>
+# CHECK-UNKNOWN: 57 94 45 4a <unknown>
vfwcvt.f.f.v v8, v4, v0.t
# CHECK-INST: vfwcvt.f.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x46,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x46,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 46 88 <unknown>
+# CHECK-UNKNOWN: 57 14 46 48 <unknown>
vfwcvt.f.f.v v8, v4
# CHECK-INST: vfwcvt.f.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x46,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x46,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 46 4a <unknown>
+
+vfwcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x47,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 47 48 <unknown>
+
+vfwcvt.rtz.xu.f.v v8, v4
+# CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x47,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 46 8a <unknown>
+# CHECK-UNKNOWN: 57 14 47 4a <unknown>
+
+vfwcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x47,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 47 48 <unknown>
+
+vfwcvt.rtz.x.f.v v8, v4
+# CHECK-INST: vfwcvt.rtz.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x47,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 47 4a <unknown>
vfncvt.xu.f.w v8, v4, v0.t
# CHECK-INST: vfncvt.xu.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x48,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 88 <unknown>
+# CHECK-UNKNOWN: 57 14 48 48 <unknown>
vfncvt.xu.f.w v8, v4
# CHECK-INST: vfncvt.xu.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x48,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 8a <unknown>
+# CHECK-UNKNOWN: 57 14 48 4a <unknown>
vfncvt.x.f.w v8, v4, v0.t
# CHECK-INST: vfncvt.x.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x48,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x48,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 48 88 <unknown>
+# CHECK-UNKNOWN: 57 94 48 48 <unknown>
vfncvt.x.f.w v8, v4
# CHECK-INST: vfncvt.x.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x48,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x48,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 48 8a <unknown>
+# CHECK-UNKNOWN: 57 94 48 4a <unknown>
vfncvt.f.xu.w v8, v4, v0.t
# CHECK-INST: vfncvt.f.xu.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x49,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x49,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 49 88 <unknown>
+# CHECK-UNKNOWN: 57 14 49 48 <unknown>
vfncvt.f.xu.w v8, v4
# CHECK-INST: vfncvt.f.xu.w v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x49,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x49,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 49 8a <unknown>
+# CHECK-UNKNOWN: 57 14 49 4a <unknown>
vfncvt.f.x.w v8, v4, v0.t
# CHECK-INST: vfncvt.f.x.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x49,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x49,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 49 88 <unknown>
+# CHECK-UNKNOWN: 57 94 49 48 <unknown>
vfncvt.f.x.w v8, v4
# CHECK-INST: vfncvt.f.x.w v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x49,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x49,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 49 8a <unknown>
+# CHECK-UNKNOWN: 57 94 49 4a <unknown>
vfncvt.f.f.w v8, v4, v0.t
# CHECK-INST: vfncvt.f.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x4a,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 4a 88 <unknown>
+# CHECK-UNKNOWN: 57 14 4a 48 <unknown>
vfncvt.f.f.w v8, v4
# CHECK-INST: vfncvt.f.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x4a,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 4a 8a <unknown>
+# CHECK-UNKNOWN: 57 14 4a 4a <unknown>
vfncvt.rod.f.f.w v8, v4, v0.t
# CHECK-INST: vfncvt.rod.f.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x4a,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x4a,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 4a 88 <unknown>
+# CHECK-UNKNOWN: 57 94 4a 48 <unknown>
vfncvt.rod.f.f.w v8, v4
# CHECK-INST: vfncvt.rod.f.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x4a,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x4a,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 4a 4a <unknown>
+
+vfncvt.rtz.xu.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.rtz.xu.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4b,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4b 48 <unknown>
+
+vfncvt.rtz.xu.f.w v8, v4
+# CHECK-INST: vfncvt.rtz.xu.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x4b,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4b 4a <unknown>
+
+vfncvt.rtz.x.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.rtz.x.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4b,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 4b 48 <unknown>
+
+vfncvt.rtz.x.f.w v8, v4
+# CHECK-INST: vfncvt.rtz.x.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x4b,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 4a 8a <unknown>
+# CHECK-UNKNOWN: 57 94 4b 4a <unknown>
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -96,25 +96,26 @@
// load vd, (rs1), vm
class VUnitStrideLoad<RISCVMOP mop, RISCVLSUMOP lumop, RISCVWidth width,
string opcodestr>
- : RVInstVLU<0b000, mop, lumop, width, (outs VRegOp:$vd),
+ : RVInstVLU<0b000, width.Value{3}, mop, lumop, width.Value{2-0},
+ (outs VRegOp:$vd),
(ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">;
// load vd, (rs1), rs2, vm
class VStridedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
- : RVInstVLS<0b000, mop, width, (outs VRegOp:$vd),
+ : RVInstVLS<0b000, width.Value{3}, mop, width.Value{2-0}, (outs VRegOp:$vd),
(ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
"$vd, (${rs1}), $rs2$vm">;
// load vd, (rs1), vs2, vm
class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
- : RVInstVLX<0b000, mop, width, (outs VRegOp:$vd),
+ : RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs VRegOp:$vd),
(ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr,
"$vd, (${rs1}), $vs2$vm">;
// vl<nf>r.v vd, (rs1)
class VWholeLoad<bits<3> nf, string opcodestr>
- : RVInstVLU<nf, MOPLDUnitStrideU, LUMOPUnitStrideWholeReg,
- LSWidthVSEW, (outs VRegOp:$vd), (ins GPR:$rs1),
+ : RVInstVLU<nf, 0b0, MOPLDUnitStride, LUMOPUnitStrideWholeReg,
+ 0b000, (outs VRegOp:$vd), (ins GPR:$rs1),
opcodestr, "$vd, (${rs1})"> {
let vm = 1;
let Uses = [];
@@ -125,26 +126,26 @@
// store vd, vs3, (rs1), vm
class VUnitStrideStore<RISCVMOP mop, RISCVLSUMOP sumop, RISCVWidth width,
string opcodestr>
- : RVInstVSU<0b000, mop, sumop, width, (outs),
+ : RVInstVSU<0b000, width.Value{3}, mop, sumop, width.Value{2-0}, (outs),
(ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
"$vs3, (${rs1})$vm">;
// store vd, vs3, (rs1), rs2, vm
class VStridedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
- : RVInstVSS<0b000, mop, width, (outs),
+ : RVInstVSS<0b000, width.Value{3}, mop, width.Value{2-0}, (outs),
(ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
opcodestr, "$vs3, (${rs1}), $rs2$vm">;
// store vd, vs3, (rs1), vs2, vm
class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
- : RVInstVSX<0b000, mop, width, (outs),
+ : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs),
(ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
opcodestr, "$vs3, (${rs1}), $vs2$vm">;
// vs<nf>r.v vd, (rs1)
class VWholeStore<bits<3> nf, string opcodestr>
- : RVInstVSU<nf, MOPSTUnitStride, SUMOPUnitStrideWholeReg,
- LSWidthVSEW, (outs), (ins VRegOp:$vs3, GPR:$rs1),
+ : RVInstVSU<nf, 0b0, MOPSTUnitStride, SUMOPUnitStrideWholeReg,
+ 0b000, (outs), (ins VRegOp:$vs3, GPR:$rs1),
opcodestr, "$vs3, (${rs1})"> {
let vm = 1;
let Uses = [];
@@ -370,68 +371,79 @@
} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
// Vector Unit-Stride Instructions
-def VLB_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVByte, "vlb.v">;
-def VLH_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVHalf, "vlh.v">;
-def VLW_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVWord, "vlw.v">;
-
-def VLBU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVByte, "vlbu.v">;
-def VLHU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVHalf, "vlhu.v">;
-def VLWU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVWord, "vlwu.v">;
-
-def VLE_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVSEW, "vle.v">;
-
-def VLBFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVByte, "vlbff.v">;
-def VLHFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVHalf, "vlhff.v">;
-def VLWFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVWord, "vlwff.v">;
-
-def VLBUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVByte, "vlbuff.v">;
-def VLHUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVHalf, "vlhuff.v">;
-def VLWUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVWord, "vlwuff.v">;
-
-def VLEFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVSEW, "vleff.v">;
-
-def VSB_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVByte, "vsb.v">;
-def VSH_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVHalf, "vsh.v">;
-def VSW_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVWord, "vsw.v">;
-
-def VSE_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVSEW, "vse.v">;
+def VLE8_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStride, LSWidth8, "vle8.v">;
+def VLE16_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStride, LSWidth16, "vle16.v">;
+def VLE32_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStride, LSWidth32, "vle32.v">;
+def VLE64_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStride, LSWidth64, "vle64.v">;
+def VLE128_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStride, LSWidth128, "vle128.v">;
+def VLE256_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStride, LSWidth256, "vle256.v">;
+def VLE512_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStride, LSWidth512, "vle512.v">;
+def VLE1024_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStride, LSWidth1024, "vle1024.v">;
+
+def VLE8FF_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStrideFF, LSWidth8, "vle8ff.v">;
+def VLE16FF_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStrideFF, LSWidth16, "vle16ff.v">;
+def VLE32FF_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStrideFF, LSWidth32, "vle32ff.v">;
+def VLE64FF_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStrideFF, LSWidth64, "vle64ff.v">;
+def VLE128FF_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStrideFF, LSWidth128, "vle128ff.v">;
+def VLE256FF_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStrideFF, LSWidth256, "vle256ff.v">;
+def VLE512FF_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStrideFF, LSWidth512, "vle512ff.v">;
+def VLE1024FF_V : VUnitStrideLoad<MOPLDUnitStride, LUMOPUnitStrideFF, LSWidth1024, "vle1024ff.v">;
+
+def VSE8_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidth8, "vse8.v">;
+def VSE16_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidth16, "vse16.v">;
+def VSE32_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidth32, "vse32.v">;
+def VSE64_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidth64, "vse64.v">;
+def VSE128_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidth128, "vse128.v">;
+def VSE256_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidth256, "vse256.v">;
+def VSE512_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidth512, "vse512.v">;
+def VSE1024_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidth1024, "vse1024.v">;
// Vector Strided Instructions
-def VLSB_V : VStridedLoad<MOPLDStridedS, LSWidthVByte, "vlsb.v">;
-def VLSH_V : VStridedLoad<MOPLDStridedS, LSWidthVHalf, "vlsh.v">;
-def VLSW_V : VStridedLoad<MOPLDStridedS, LSWidthVWord, "vlsw.v">;
-
-def VLSBU_V : VStridedLoad<MOPLDStridedU, LSWidthVByte, "vlsbu.v">;
-def VLSHU_V : VStridedLoad<MOPLDStridedU, LSWidthVHalf, "vlshu.v">;
-def VLSWU_V : VStridedLoad<MOPLDStridedU, LSWidthVWord, "vlswu.v">;
-
-def VLSE_V : VStridedLoad<MOPLDStridedU, LSWidthVSEW, "vlse.v">;
-
-def VSSB_V : VStridedStore<MOPSTStrided, LSWidthVByte, "vssb.v">;
-def VSSH_V : VStridedStore<MOPSTStrided, LSWidthVHalf, "vssh.v">;
-def VSSW_V : VStridedStore<MOPSTStrided, LSWidthVWord, "vssw.v">;
-def VSSE_V : VStridedStore<MOPSTStrided, LSWidthVSEW, "vsse.v">;
+def VLSE8_V : VStridedLoad<MOPLDStrided, LSWidth8, "vlse8.v">;
+def VLSE16_V : VStridedLoad<MOPLDStrided, LSWidth16, "vlse16.v">;
+def VLSE32_V : VStridedLoad<MOPLDStrided, LSWidth32, "vlse32.v">;
+def VLSE64_V : VStridedLoad<MOPLDStrided, LSWidth64, "vlse64.v">;
+def VLSE128_V : VStridedLoad<MOPLDStrided, LSWidth128, "vlse128.v">;
+def VLSE256_V : VStridedLoad<MOPLDStrided, LSWidth256, "vlse256.v">;
+def VLSE512_V : VStridedLoad<MOPLDStrided, LSWidth512, "vlse512.v">;
+def VLSE1024_V : VStridedLoad<MOPLDStrided, LSWidth1024, "vlse1024.v">;
+
+def VSSE8_V : VStridedStore<MOPSTStrided, LSWidth8, "vsse8.v">;
+def VSSE16_V : VStridedStore<MOPSTStrided, LSWidth16, "vsse16.v">;
+def VSSE32_V : VStridedStore<MOPSTStrided, LSWidth32, "vsse32.v">;
+def VSSE64_V : VStridedStore<MOPSTStrided, LSWidth64, "vsse64.v">;
+def VSSE128_V : VStridedStore<MOPSTStrided, LSWidth128, "vsse128.v">;
+def VSSE256_V : VStridedStore<MOPSTStrided, LSWidth256, "vsse256.v">;
+def VSSE512_V : VStridedStore<MOPSTStrided, LSWidth512, "vsse512.v">;
+def VSSE1024_V : VStridedStore<MOPSTStrided, LSWidth1024, "vsse1024.v">;
// Vector Indexed Instructions
-def VLXB_V : VIndexedLoad<MOPLDIndexedS, LSWidthVByte, "vlxb.v">;
-def VLXH_V : VIndexedLoad<MOPLDIndexedS, LSWidthVHalf, "vlxh.v">;
-def VLXW_V : VIndexedLoad<MOPLDIndexedS, LSWidthVWord, "vlxw.v">;
-
-def VLXBU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVByte, "vlxbu.v">;
-def VLXHU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVHalf, "vlxhu.v">;
-def VLXWU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVWord, "vlxwu.v">;
-
-def VLXE_V : VIndexedLoad<MOPLDIndexedU, LSWidthVSEW, "vlxe.v">;
-
-def VSXB_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVByte, "vsxb.v">;
-def VSXH_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVHalf, "vsxh.v">;
-def VSXW_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVWord, "vsxw.v">;
-def VSXE_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVSEW, "vsxe.v">;
-
-def VSUXB_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVByte, "vsuxb.v">;
-def VSUXH_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVHalf, "vsuxh.v">;
-def VSUXW_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVWord, "vsuxw.v">;
-def VSUXE_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVSEW, "vsuxe.v">;
+def VLXEI8_V : VIndexedLoad<MOPLDIndexed, LSWidth8, "vlxei8.v">;
+def VLXEI16_V : VIndexedLoad<MOPLDIndexed, LSWidth16, "vlxei16.v">;
+def VLXEI32_V : VIndexedLoad<MOPLDIndexed, LSWidth32, "vlxei32.v">;
+def VLXEI64_V : VIndexedLoad<MOPLDIndexed, LSWidth64, "vlxei64.v">;
+def VLXEI128_V : VIndexedLoad<MOPLDIndexed, LSWidth128, "vlxei128.v">;
+def VLXEI256_V : VIndexedLoad<MOPLDIndexed, LSWidth256, "vlxei256.v">;
+def VLXEI512_V : VIndexedLoad<MOPLDIndexed, LSWidth512, "vlxei512.v">;
+def VLXEI1024_V : VIndexedLoad<MOPLDIndexed, LSWidth1024, "vlxei1024.v">;
+
+def VSXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsxei8.v">;
+def VSXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsxei16.v">;
+def VSXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsxei32.v">;
+def VSXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsxei64.v">;
+def VSXEI128_V : VIndexedStore<MOPSTIndexedOrder, LSWidth128, "vsxei128.v">;
+def VSXEI256_V : VIndexedStore<MOPSTIndexedOrder, LSWidth256, "vsxei256.v">;
+def VSXEI512_V : VIndexedStore<MOPSTIndexedOrder, LSWidth512, "vsxei512.v">;
+def VSXEI1024_V : VIndexedStore<MOPSTIndexedOrder, LSWidth1024, "vsxei1024.v">;
+
+def VSUXEI8_V : VIndexedStore<MOPSTIndexedUnord, LSWidth8, "vsuxei8.v">;
+def VSUXEI16_V : VIndexedStore<MOPSTIndexedUnord, LSWidth16, "vsuxei16.v">;
+def VSUXEI32_V : VIndexedStore<MOPSTIndexedUnord, LSWidth32, "vsuxei32.v">;
+def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">;
+def VSUXEI128_V : VIndexedStore<MOPSTIndexedUnord, LSWidth128, "vsuxei128.v">;
+def VSUXEI256_V : VIndexedStore<MOPSTIndexedUnord, LSWidth256, "vsuxei256.v">;
+def VSUXEI512_V : VIndexedStore<MOPSTIndexedUnord, LSWidth512, "vsuxei512.v">;
+def VSUXEI1024_V : VIndexedStore<MOPSTIndexedUnord, LSWidth1024, "vsuxei1024.v">;
def VL1R_V : VWholeLoad<0, "vl1r.v">;
def VS1R_V : VWholeStore<0, "vs1r.v">;
@@ -470,6 +482,14 @@
def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm",
(VWADDU_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>;
+// Vector Integer Extension
+defm VZEXT_VF8 : VALU_MV_VS2<"vzext.vf8", 0b010010, 0b00010>;
+defm VSEXT_VF8 : VALU_MV_VS2<"vsext.vf8", 0b010010, 0b00011>;
+defm VZEXT_VF4 : VALU_MV_VS2<"vzext.vf4", 0b010010, 0b00100>;
+defm VSEXT_VF4 : VALU_MV_VS2<"vsext.vf4", 0b010010, 0b00101>;
+defm VZEXT_VF2 : VALU_MV_VS2<"vzext.vf2", 0b010010, 0b00110>;
+defm VSEXT_VF2 : VALU_MV_VS2<"vsext.vf2", 0b010010, 0b00111>;
+
// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;
defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
@@ -662,7 +682,7 @@
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
// Vector Floating-Point Square-Root Instruction
-defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>;
+defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>;
// Vector Floating-Point MIN/MAX Instructions
defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>;
@@ -687,7 +707,7 @@
(VMFLE_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
// Vector Floating-Point Classify Instruction
-defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b100011, 0b10000>;
+defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b010011, 0b10000>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// Vector Floating-Point Merge Instruction
@@ -706,28 +726,34 @@
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
// Single-Width Floating-Point/Integer Type-Convert Instructions
-defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>;
-defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>;
-defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>;
-defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>;
+defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>;
+defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>;
+defm VFCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>;
+defm VFCVT_RTZ_X_F_V : VALU_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>;
+defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>;
+defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>;
// Widening Floating-Point/Integer Type-Convert Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in {
-defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>;
-defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>;
-defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>;
-defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>;
-defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>;
+defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>;
+defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>;
+defm VFWCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>;
+defm VFWCVT_RTZ_X_F_V : VALU_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>;
+defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>;
+defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>;
+defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt
// Narrowing Floating-Point/Integer Type-Convert Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = NarrowCvt in {
-defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b100010, 0b10000>;
-defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b100010, 0b10001>;
-defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b100010, 0b10010>;
-defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b100010, 0b10011>;
-defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b100010, 0b10100>;
-defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b100010, 0b10101>;
+defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>;
+defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>;
+defm VFNCVT_RTZ_XU_F_W : VALU_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>;
+defm VFNCVT_RTZ_X_F_W : VALU_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>;
+defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>;
+defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>;
+defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>;
+defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = NarrowCvt
// Vector Single-Width Integer Reduction Instructions
@@ -776,7 +802,7 @@
defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">;
defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">;
-def : InstAlias<"vmcpy.m $vd, $vs",
+def : InstAlias<"vmmv.m $vd, $vs",
(VMAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>;
def : InstAlias<"vmclr.m $vd",
(VMXOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>;
@@ -845,8 +871,10 @@
let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>;
+defm VFSLIDE1UP_V : VALU_FV_F<"vfslide1up", 0b001110>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>;
+defm VFSLIDE1DOWN_V : VALU_FV_F<"vfslide1down", 0b001111>;
// Vector Register Gather Instruction
let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
Index: llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+++ llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -21,20 +21,17 @@
def OPFVF : RISCVVFormat<0b101>;
def OPMVX : RISCVVFormat<0b110>;
-class RISCVMOP<bits<3> val> {
- bits<3> Value = val;
+class RISCVMOP<bits<2> val> {
+ bits<2> Value = val;
}
-def MOPLDUnitStrideU : RISCVMOP<0b000>;
-def MOPLDStridedU : RISCVMOP<0b010>;
-def MOPLDIndexedU : RISCVMOP<0b011>;
-def MOPLDUnitStrideS : RISCVMOP<0b100>;
-def MOPLDStridedS : RISCVMOP<0b110>;
-def MOPLDIndexedS : RISCVMOP<0b111>;
-
-def MOPSTUnitStride : RISCVMOP<0b000>;
-def MOPSTStrided : RISCVMOP<0b010>;
-def MOPSTIndexedOrder: RISCVMOP<0b011>;
-def MOPSTIndexedUnOrd: RISCVMOP<0b111>;
+def MOPLDUnitStride : RISCVMOP<0b00>;
+def MOPLDStrided : RISCVMOP<0b10>;
+def MOPLDIndexed : RISCVMOP<0b11>;
+
+def MOPSTUnitStride : RISCVMOP<0b00>;
+def MOPSTIndexedUnord : RISCVMOP<0b01>;
+def MOPSTStrided : RISCVMOP<0b10>;
+def MOPSTIndexedOrder : RISCVMOP<0b11>;
class RISCVLSUMOP<bits<5> val> {
bits<5> Value = val;
@@ -45,13 +42,17 @@
def SUMOPUnitStride : RISCVLSUMOP<0b00000>;
def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
-class RISCVWidth<bits<3> val> {
- bits<3> Value = val;
+class RISCVWidth<bits<4> val> {
+ bits<4> Value = val;
}
-def LSWidthVByte : RISCVWidth<0b000>;
-def LSWidthVHalf : RISCVWidth<0b101>;
-def LSWidthVWord : RISCVWidth<0b110>;
-def LSWidthVSEW : RISCVWidth<0b111>;
+def LSWidth8 : RISCVWidth<0b0000>;
+def LSWidth16 : RISCVWidth<0b0101>;
+def LSWidth32 : RISCVWidth<0b0110>;
+def LSWidth64 : RISCVWidth<0b0111>;
+def LSWidth128 : RISCVWidth<0b1000>;
+def LSWidth256 : RISCVWidth<0b1101>;
+def LSWidth512 : RISCVWidth<0b1110>;
+def LSWidth1024 : RISCVWidth<0b1111>;
class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
@@ -179,8 +180,8 @@
let Uses = [VTYPE, VL];
}
-class RVInstVLU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP lumop,
- RISCVWidth width, dag outs, dag ins, string opcodestr,
+class RVInstVLU<bits<3> nf, bit mew, RISCVMOP mop, RISCVLSUMOP lumop,
+ bits<3> width, dag outs, dag ins, string opcodestr,
string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs1;
@@ -188,18 +189,19 @@
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = mop.Value;
let Inst{25} = vm;
let Inst{24-20} = lumop.Value;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vd;
let Opcode = OPC_LOAD_FP.Value;
let Uses = [VTYPE, VL];
}
-class RVInstVLS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVLS<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs2;
@@ -208,18 +210,19 @@
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = mop.Value;
let Inst{25} = vm;
let Inst{24-20} = rs2;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vd;
let Opcode = OPC_LOAD_FP.Value;
let Uses = [VTYPE, VL];
}
-class RVInstVLX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> vs2;
@@ -228,19 +231,20 @@
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = mop.Value;
let Inst{25} = vm;
let Inst{24-20} = vs2;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vd;
let Opcode = OPC_LOAD_FP.Value;
let Uses = [VTYPE, VL];
}
-class RVInstVSU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP sumop,
- RISCVWidth width, dag outs, dag ins, string opcodestr,
+class RVInstVSU<bits<3> nf, bit mew, RISCVMOP mop, RISCVLSUMOP sumop,
+ bits<3> width, dag outs, dag ins, string opcodestr,
string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs1;
@@ -248,18 +252,19 @@
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = mop.Value;
let Inst{25} = vm;
let Inst{24-20} = sumop.Value;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vs3;
let Opcode = OPC_STORE_FP.Value;
let Uses = [VTYPE, VL];
}
-class RVInstVSS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVSS<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs2;
@@ -268,18 +273,19 @@
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = mop.Value;
let Inst{25} = vm;
let Inst{24-20} = rs2;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vs3;
let Opcode = OPC_STORE_FP.Value;
let Uses = [VTYPE, VL];
}
-class RVInstVSX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> vs2;
@@ -288,11 +294,12 @@
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = mop.Value;
let Inst{25} = vm;
let Inst{24-20} = vs2;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vs3;
let Opcode = OPC_STORE_FP.Value;
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -155,10 +155,30 @@
unsigned Imm = MI->getOperand(OpNo).getImm();
unsigned Sew = (Imm >> 2) & 0x7;
unsigned Lmul = Imm & 0x3;
+ bool Fractional = (Imm >> 5) & 0x1;
- Lmul = 0x1 << Lmul;
Sew = 0x1 << (Sew + 3);
- O << "e" << Sew << ",m" << Lmul;
+ O << "e" << Sew;
+ if (Fractional) {
+ Lmul = 4 - Lmul;
+ Lmul = 0x1 << Lmul;
+ O << ",mf" << Lmul;
+ } else {
+ Lmul = 0x1 << Lmul;
+ O << ",m" << Lmul;
+ }
+ bool TailAgnostic = Imm & 0x40;
+ bool MaskedoffAgnostic = Imm & 0x80;
+ if (TailAgnostic || MaskedoffAgnostic) {
+ if (TailAgnostic)
+ O << ",ta";
+ else
+ O << ",tu";
+ if (MaskedoffAgnostic)
+ O << ",ma";
+ else
+ O << ",mu";
+ }
}
void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -288,11 +288,21 @@
SEW_1024,
};
- enum class VLMUL { LMUL_1 = 0, LMUL_2, LMUL_4, LMUL_8 };
+ enum class VLMUL {
+ LMUL_1 = 0,
+ LMUL_2,
+ LMUL_4,
+ LMUL_8,
+ LMUL_F8 = 5,
+ LMUL_F4 = 6,
+ LMUL_F2 = 7
+ };
struct VTypeOp {
VSEW Sew;
VLMUL Lmul;
+ bool TailAgnostic;
+ bool MaskedoffAgnostic;
unsigned Encoding;
};
@@ -775,6 +785,12 @@
return "m4";
case VLMUL::LMUL_8:
return "m8";
+ case VLMUL::LMUL_F2:
+ return "mf2";
+ case VLMUL::LMUL_F4:
+ return "mf4";
+ case VLMUL::LMUL_F8:
+ return "mf8";
}
}
@@ -850,15 +866,31 @@
return Op;
}
- static std::unique_ptr<RISCVOperand> createVType(APInt Sew, APInt Lmul,
- SMLoc S, bool IsRV64) {
+ static std::unique_ptr<RISCVOperand>
+ createVType(APInt Sew, APInt Lmul, bool Fractional, bool TailAgnostic,
+ bool MaskedoffAgnostic, SMLoc S, bool IsRV64) {
auto Op = std::make_unique<RISCVOperand>(KindTy::VType);
Sew.ashrInPlace(3);
unsigned SewLog2 = Sew.logBase2();
unsigned LmulLog2 = Lmul.logBase2();
Op->VType.Sew = static_cast<VSEW>(SewLog2);
- Op->VType.Lmul = static_cast<VLMUL>(LmulLog2);
- Op->VType.Encoding = (SewLog2 << 2) | LmulLog2;
+ if (Fractional) {
+ unsigned Flmul = 8 - LmulLog2;
+ Op->VType.Lmul = static_cast<VLMUL>(Flmul);
+ Op->VType.Encoding =
+ ((Flmul & 0x4) << 3) | ((SewLog2 & 0x7) << 2) | (Flmul & 0x3);
+ } else {
+ Op->VType.Lmul = static_cast<VLMUL>(LmulLog2);
+ Op->VType.Encoding = (SewLog2 << 2) | LmulLog2;
+ }
+ if (TailAgnostic) {
+ Op->VType.Encoding |= 0x40;
+ }
+ if (MaskedoffAgnostic) {
+ Op->VType.Encoding |= 0x80;
+ }
+ Op->VType.TailAgnostic = TailAgnostic;
+ Op->VType.MaskedoffAgnostic = MaskedoffAgnostic;
Op->StartLoc = S;
Op->IsRV64 = IsRV64;
return Op;
@@ -1178,8 +1210,10 @@
}
case Match_InvalidVTypeI: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
- return Error(ErrorLoc,
- "operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]");
+ return Error(
+ ErrorLoc,
+ "operand must be "
+ "e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
}
case Match_InvalidVMaskRegister: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
@@ -1557,8 +1591,8 @@
getLexer().Lex();
if (getLexer().getKind() == AsmToken::EndOfStatement) {
- Operands.push_back(
- RISCVOperand::createVType(Sew, APInt(16, 1), S, isRV64()));
+ Operands.push_back(RISCVOperand::createVType(Sew, APInt(16, 1), false,
+ false, false, S, isRV64()));
return MatchOperand_Success;
}
@@ -1570,15 +1604,63 @@
Name = getLexer().getTok().getIdentifier();
if (!Name.consume_front("m"))
return MatchOperand_NoMatch;
+ // "m" or "mf"
+ bool Fractional = false;
+ if (Name.consume_front("f")) {
+ Fractional = true;
+ }
APInt Lmul(16, Name, 10);
if (Lmul != 1 && Lmul != 2 && Lmul != 4 && Lmul != 8)
return MatchOperand_NoMatch;
getLexer().Lex();
+ if (getLexer().getKind() == AsmToken::EndOfStatement) {
+ Operands.push_back(RISCVOperand::createVType(Sew, Lmul, Fractional, false,
+ false, S, isRV64()));
+ return MatchOperand_Success;
+ }
+
+ if (!getLexer().is(AsmToken::Comma))
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
+ Name = getLexer().getTok().getIdentifier();
+ // ta or tu
+ bool TailAgnostic = false;
+ if (Name.consume_front("ta"))
+ TailAgnostic = true;
+ else if (Name.consume_front("tu"))
+ TailAgnostic = false;
+ else
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
+ if (getLexer().getKind() == AsmToken::EndOfStatement) {
+ Operands.push_back(RISCVOperand::createVType(
+ Sew, Lmul, Fractional, TailAgnostic, false, S, isRV64()));
+ return MatchOperand_Success;
+ }
+
+ if (!getLexer().is(AsmToken::Comma))
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
+ Name = getLexer().getTok().getIdentifier();
+ // ma or mu
+ bool MaskedoffAgnostic = false;
+ if (Name.consume_front("ma"))
+ MaskedoffAgnostic = true;
+ else if (Name.consume_front("mu"))
+ MaskedoffAgnostic = false;
+ else
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
if (getLexer().getKind() != AsmToken::EndOfStatement)
return MatchOperand_NoMatch;
- Operands.push_back(RISCVOperand::createVType(Sew, Lmul, S, isRV64()));
+ Operands.push_back(RISCVOperand::createVType(
+ Sew, Lmul, Fractional, TailAgnostic, MaskedoffAgnostic, S, isRV64()));
return MatchOperand_Success;
}
@@ -2288,26 +2370,12 @@
if (DestReg == Src2Reg)
return Error(Loc, "The destination vector register group cannot overlap"
" the source vector register group.");
- if (TargetFlags == RISCV::WidenV) {
- // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
- if (DestReg + 1 == Src2Reg)
- return Error(Loc,
- "The destination vector register group cannot overlap"
- " the source vector register group.");
- }
}
if (Inst.getOperand(2).isReg()) {
unsigned Src1Reg = Inst.getOperand(2).getReg();
if (DestReg == Src1Reg)
return Error(Loc, "The destination vector register group cannot overlap"
" the source vector register group.");
- if (TargetFlags == RISCV::WidenV || TargetFlags == RISCV::WidenW) {
- // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
- if (DestReg + 1 == Src1Reg)
- return Error(Loc,
- "The destination vector register group cannot overlap"
- " the source vector register group.");
- }
}
if (Inst.getNumOperands() == 4) {
unsigned MaskReg = Inst.getOperand(3).getReg();
@@ -2321,28 +2389,12 @@
if (DestReg == Src2Reg)
return Error(Loc, "The destination vector register group cannot overlap"
" the source vector register group.");
- // Assume Src2Reg LMUL is 2 at least for widening/narrowing operations.
- if (DestReg == Src2Reg + 1)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the source vector register group.");
} else if (TargetFlags == RISCV::WidenCvt ||
TargetFlags == RISCV::NarrowCvt || TargetFlags == RISCV::Iota) {
unsigned Src2Reg = Inst.getOperand(1).getReg();
if (DestReg == Src2Reg)
return Error(Loc, "The destination vector register group cannot overlap"
" the source vector register group.");
- if (TargetFlags == RISCV::WidenCvt) {
- // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
- if (DestReg + 1 == Src2Reg)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the source vector register group.");
- }
- if (TargetFlags == RISCV::NarrowCvt) {
- // Assume Src2Reg LMUL is 2 at least for widening/narrowing operations.
- if (DestReg == Src2Reg + 1)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the source vector register group.");
- }
if (Inst.getNumOperands() == 3) {
unsigned MaskReg = Inst.getOperand(2).getReg();
Index: clang/test/Driver/riscv-arch.c
===================================================================
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -376,6 +376,6 @@
// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p8 -menable-experimental-extensions -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===================================================================
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,7 +63,7 @@
Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
return RISCVExtensionVersion{"0", "92"};
if (Ext == "v")
- return RISCVExtensionVersion{"0", "8"};
+ return RISCVExtensionVersion{"0", "9"};
return None;
}
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