kmclaughlin added inline comments.
================
Comment at: clang/test/CodeGen/aarch64-v8.6a-neon-intrinsics.c:3
+// RUN: -fallow-half-arguments-and-returns -S -disable-O0-optnone -emit-llvm
-o - %s \
+// RUN: | opt -S -mem2reg \
+// RUN: | FileCheck %s
----------------
Is it possible to use -sroa here as you did for the tests added in D77872? If
so, I think this might make some of the `_lane` tests below a bit easier to
follow.
================
Comment at: llvm/test/MC/AArch64/armv8.6a-simd-matmul-error.s:17
+// For USDOT and SUDOT (indexed), the index is in range [0,3] (regardless of
data types)
+usdot v31.2s, v1.8b, v2.4b[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in
range [0, 3].
----------------
The arrangement specifiers of the first two operands don't match for these
tests, which is what the next set of tests below is checking for. It might be
worth keeping these tests specific to just the index being out of range.
================
Comment at: llvm/test/MC/AArch64/armv8.6a-simd-matmul-error.s:26
+
+// The arrangement specifiers of the first two operands muct match.
+usdot v31.4s, v1.8b, v2.4b[0]
----------------
muct -> must :)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D77871/new/
https://reviews.llvm.org/D77871
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