ZarkoCA updated this revision to Diff 252147.
ZarkoCA added a comment.
Simplified testcases.
Added testcases for variadic arguments being passed directly to the stack when
all registers are used.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D76130/new/
https://reviews.llvm.org/D76130
Files:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
Index: llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
@@ -0,0 +1,224 @@
+; RUN: llc -O2 -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
+
+; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefixes=CHECKASM,ASM64PWR4 %s
+
+ target datalayout = "E-m:e-i64:64-n32:64"
+ target triple = "powerpc64-ibm-aix-xcoff"
+
+ define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr {
+ entry:
+ %arg = alloca i8*, align 8
+ %0 = bitcast i8** %arg to i8*
+ call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+ call void @llvm.va_start(i8* nonnull %0)
+ call void @llvm.va_copy(i8* nonnull %0, i8* nonnull %0)
+ %1 = va_arg i8** %arg, i32
+ %add = add nsw i32 %1, %a
+ call void @llvm.va_end(i8* nonnull %0)
+ call void @llvm.va_end(i8* nonnull %0)
+ call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+ ret i32 %add
+ }
+
+ declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+ declare void @llvm.va_start(i8*)
+ declare void @llvm.va_copy(i8*, i8*)
+ declare void @llvm.va_end(i8*)
+ declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+
+ define i32 @int_stack_va_arg(i32 %one, i32 %two, i32 %three, i32 %four, i32 %five, i32 %six, i32 %seven, i32 %eight, ...) local_unnamed_addr {
+ entry:
+ %arg = alloca i8*, align 8
+ %0 = bitcast i8** %arg to i8*
+ call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+ call void @llvm.va_start(i8* nonnull %0)
+ %add = add nsw i32 %two, %one
+ %add3 = add nsw i32 %add, %three
+ %add4 = add nsw i32 %add3, %four
+ %add5 = add nsw i32 %add4, %five
+ %add6 = add nsw i32 %add5, %six
+ %add7 = add nsw i32 %add6, %seven
+ %add8 = add nsw i32 %add7, %eight
+ %1 = va_arg i8** %arg, i32
+ %add9 = add nsw i32 %add8, %1
+ call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+ ret i32 %add9
+ }
+
+ define double @double_va_arg(double %a, ...) local_unnamed_addr {
+ entry:
+ %arg = alloca i8*, align 8
+ %0 = bitcast i8** %arg to i8*
+ call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+ call void @llvm.va_start(i8* nonnull %0)
+ call void @llvm.va_copy(i8* nonnull %0, i8* nonnull %0)
+ %1 = va_arg i8** %arg, double
+ %add = fadd double %1, %a
+ call void @llvm.va_end(i8* nonnull %0)
+ call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+ ret double %add
+ }
+
+ define double @double_stack_va_arg(double %one, double %two, double %three, double %four, double %five, double %six, double %seven, double %eight, double %nine, double %ten, double %eleven, double %twelve, double %thirtheen, ...) local_unnamed_addr {
+ entry:
+ %arg = alloca i8*, align 8
+ %0 = bitcast i8** %arg to i8*
+ call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+ call void @llvm.va_start(i8* nonnull %0)
+ %add = fadd double %one, %two
+ %add3 = fadd double %add, %three
+ %add4 = fadd double %add3, %four
+ %add5 = fadd double %add4, %five
+ %add6 = fadd double %add5, %six
+ %add7 = fadd double %add6, %seven
+ %add8 = fadd double %add7, %eight
+ %1 = va_arg i8** %arg, double
+ %add9 = fadd double %add8, %1
+ call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+ ret double %add9
+ }
+
+ declare void @llvm.stackprotector(i8*, i8**)
+
+; CHECK-LABEL: name: int_va_arg
+; CHECK-LABEL: liveins:
+; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x4', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x5', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x6', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x7', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x8', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x9', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x10', virtual-reg: '' }
+
+; CHECK-LABEL: fixedStack:
+; 64BIT: - { id: 0, type: default, offset: 56, size: 8
+; CHECK-LABEL: body: |
+; 64BIT: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+; 64BIT-DAG: STD killed renamable $x4, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0)
+; 64BIT-DAG: STD killed renamable $x5, 8, %fixed-stack.0 :: (store 8 into %fixed-stack.0 + 8)
+; 64BIT-DAG: STD killed renamable $x6, 16, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x7, 24, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x8, 32, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x9, 40, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x10, 48, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: renamable $r11 = LWZ 0, %fixed-stack.0 :: (load 4 from %fixed-stack.0, align 8)
+; 64BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r11, renamable $r3, implicit killed $x3, implicit-def $x3
+; 64BIT-DAG: BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+; CHECKASM-LABEL: .int_va_arg:
+; ASM64-DAG: lwz 11, 56(1)
+; ASM64-DAG: add 3, 11, 3
+; ASM64-DAG: std 4, 56(1)
+; ASM64-DAG: std 5, 64(1)
+; ASM64-DAG: std 6, 72(1)
+; ASM64-DAG: std 7, 80(1)
+; ASM64-DAG: std 8, 88(1)
+; ASM64-DAG: std 9, 96(1)
+; ASM64-DAG: std 10, 104(1)
+; ASM64-DAG: blr
+
+; CHECK-LABEL: name: int_stack_va_arg
+; CHECK-LABEL: liveins:
+; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x4', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x5', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x6', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x7', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x8', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x9', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x10', virtual-reg: '' }
+; CHECK-LABEL: fixedStack:
+; 64BIT: - { id: 0, type: default, offset: 112, size: 8
+
+; CHECK-LABEL: body: |
+; 64BIT: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+; 64BIT-DAG: renamable $r3 = nsw ADD4 renamable $r4, renamable $r3, implicit killed $x3, implicit killed $x4
+; 64BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5
+; 64BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r6, implicit killed $x6
+; 64BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r7, implicit killed $x7
+; 64BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r8, implicit killed $x8
+; 64BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r9, implicit killed $x9
+; 64BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r10, implicit killed $x10
+; 64BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r11, implicit-def $x3
+; 64BIT-DAG: renamable $r11 = LWZ 0, %fixed-stack.0 :: (load 4 from %fixed-stack.0, align 16)
+; 64BIT-DAG: BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+; CHECKASM-LABEL: .int_stack_va_arg:
+; ASM64-DAG: add 3, 4, 3
+; ASM64-DAG: add 3, 3, 5
+; ASM64-DAG: add 3, 3, 6
+; ASM64-DAG: add 3, 3, 7
+; ASM64-DAG: add 3, 3, 8
+; ASM64-DAG: add 3, 3, 9
+; ASM64-DAG: add 3, 3, 10
+; ASM64-DAG: lwz 11, 112(1)
+; ASM64-DAG: add 3, 3, 11
+; ASM64-DAG: blr
+
+; CHECK-LABEL: name: double_va_arg
+; CHECK-LABEL: liveins:
+; 64BIT-NEXT: - { reg: '$f1', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x4', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x5', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x6', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x7', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x8', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x9', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x10', virtual-reg: '' }
+; CHECK-LABEL: fixedStack:
+; 64BIT: - { id: 0, type: default, offset: 56, size: 8
+
+; CHECK-LABEL: body: |
+; 64BIT: liveins: $f1, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+; 64BIT-DAG: STD killed renamable $x4, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0)
+; 64BIT-DAG: STD killed renamable $x5, 8, %fixed-stack.0 :: (store 8 into %fixed-stack.0 + 8)
+; 64BIT-DAG: STD killed renamable $x6, 16, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x7, 24, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x8, 32, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x9, 40, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: STD killed renamable $x10, 48, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG: renamable $f0 = LFD 0, %fixed-stack.0 :: (load 8)
+; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
+; 64BIT-DAG: BLR8 implicit $lr8, implicit $rm, implicit $f1
+
+; CHECK-LABEL: name: double_stack_va_arg
+; CHECK-LABEL: liveins:
+; 64BIT-NEXT: - { reg: '$f1', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f2', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f3', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f4', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f5', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f6', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f7', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f8', virtual-reg: '' }
+; CHECK-LABEL: fixedStack:
+; 64BIT: - { id: 0, type: default, offset: 152, size: 8
+
+; CHECK-LABEL: body: |
+; 64BIT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8
+; 64BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
+; 64BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f3, implicit $rm
+; 64BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f4, implicit $rm
+; 64BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f5, implicit $rm
+; 64BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f6, implicit $rm
+; 64BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f7, implicit $rm
+; 64BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f8, implicit $rm
+; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f[[SCRATCHREG:[0-9]+]], implicit $rm
+; 64BIT-DAG: renamable $f[[DBLREG:[0-9]+]] = LFD 0, %fixed-stack.0 :: (load 8)
+; 64BIT-DAG: BLR8 implicit $lr8, implicit $rm, implicit $f1
+
+; CHECKASM-LABEL: .double_stack_va_arg:
+; ASM64-DAG: fadd [[SCRATCHREG:[0-9]+]], 1, 2
+; ASM64-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 3
+; ASM64-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 4
+; ASM64-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 5
+; ASM64-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 6
+; ASM64-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 7
+; ASM64-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 8
+; ASM64-DAG: lfd [[DBLREG:[0-9]+]], 152(1)
+; ASM64-DAG: fadd [[DBLREG]], [[SCRATCHREG:[0-9]+]], 1
+; ASM64-DAG: blr
Index: llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
@@ -0,0 +1,246 @@
+; RUN: llc -O2 -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
+
+; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefixes=CHECKASM,ASM32 %s
+
+ target datalayout = "E-m:e-p:32:32-i64:64-n32"
+ target triple = "powerpc-ibm-aix-xcoff"
+
+ define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr {
+ entry:
+ %arg = alloca i8*, align 4
+ %0 = bitcast i8** %arg to i8*
+ call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
+ call void @llvm.va_start(i8* nonnull %0)
+ call void @llvm.va_copy(i8* nonnull %0, i8* nonnull %0)
+ %argp.cur = load i8*, i8** %arg, align 4
+ %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
+ store i8* %argp.next, i8** %arg, align 4
+ %1 = bitcast i8* %argp.cur to i32*
+ %2 = load i32, i32* %1, align 4
+ %add = add nsw i32 %2, %a
+ call void @llvm.va_end(i8* nonnull %0)
+ call void @llvm.va_end(i8* nonnull %0)
+ call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
+ ret i32 %add
+ }
+ declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+ declare void @llvm.va_start(i8*)
+ declare void @llvm.va_copy(i8*, i8*)
+ declare void @llvm.va_end(i8*)
+ declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+
+ define i32 @int_stack_va_arg(i32 %one, i32 %two, i32 %three, i32 %four, i32 %five, i32 %six, i32 %seven, i32 %eight, ...) local_unnamed_addr {
+ entry:
+ %arg = alloca i8*, align 4
+ %0 = bitcast i8** %arg to i8*
+ call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
+ call void @llvm.va_start(i8* nonnull %0)
+ %add = add nsw i32 %two, %one
+ %add3 = add nsw i32 %add, %three
+ %add4 = add nsw i32 %add3, %four
+ %add5 = add nsw i32 %add4, %five
+ %add6 = add nsw i32 %add5, %six
+ %add7 = add nsw i32 %add6, %seven
+ %add8 = add nsw i32 %add7, %eight
+ %argp.cur = load i8*, i8** %arg, align 4
+ %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
+ store i8* %argp.next, i8** %arg, align 4
+ %1 = bitcast i8* %argp.cur to i32*
+ %2 = load i32, i32* %1, align 4
+ %add9 = add nsw i32 %add8, %2
+ call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
+ ret i32 %add9
+ }
+
+ define double @double_va_arg(double %a, ...) local_unnamed_addr {
+ entry:
+ %arg = alloca i8*, align 4
+ %0 = bitcast i8** %arg to i8*
+ call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
+ call void @llvm.va_start(i8* nonnull %0)
+ call void @llvm.va_copy(i8* nonnull %0, i8* nonnull %0)
+ %argp.cur = load i8*, i8** %arg, align 4
+ %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 8
+ store i8* %argp.next, i8** %arg, align 4
+ %1 = bitcast i8* %argp.cur to double*
+ %2 = load double, double* %1, align 4
+ %add = fadd double %2, %a
+ call void @llvm.va_end(i8* nonnull %0)
+ call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
+ ret double %add
+ }
+
+ define double @double_stack_va_arg(double %one, double %two, double %three, double %four, double %five, double %six, double %seven, double %eight, ...) local_unnamed_addr {
+ entry:
+ %arg = alloca i8*, align 4
+ %0 = bitcast i8** %arg to i8*
+ call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
+ call void @llvm.va_start(i8* nonnull %0)
+ %add = fadd double %one, %two
+ %add3 = fadd double %add, %three
+ %add4 = fadd double %add3, %four
+ %add5 = fadd double %add4, %five
+ %add6 = fadd double %add5, %six
+ %add7 = fadd double %add6, %seven
+ %add8 = fadd double %add7, %eight
+ %1 = bitcast i8** %arg to double**
+ %argp.cur10 = load double*, double** %1, align 4
+ %2 = load double, double* %argp.cur10, align 4
+ %add9 = fadd double %add8, %2
+ call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
+ ret double %add9
+ }
+
+ declare void @llvm.stackprotector(i8*, i8**)
+
+; CHECK-LABEL: name: int_va_arg
+; CHECK-LABEL: liveins:
+; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r4', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r5', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r6', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r7', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r8', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r9', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r10', virtual-reg: '' }
+
+; CHECK-LABEL: fixedStack:
+; 32BIT: - { id: 0, type: default, offset: 28, size: 4
+; CHECK-LABEL: body: |
+; 32BIT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
+; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r4, killed renamable $r3
+; 32BIT-DAG: STW renamable $r4, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0)
+; 32BIT-DAG: STW killed renamable $r5, 4, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 4)
+; 32BIT-DAG: STW killed renamable $r6, 8, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r7, 12, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r8, 16, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r9, 20, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r10, 24, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $r3
+
+; CHECKASM-LABEL: .int_va_arg:
+; ASM32-DAG: add 3, 4, 3
+; ASM32-DAG: stw 4, 28(1)
+; ASM32-DAG: stw 5, 32(1)
+; ASM32-DAG: stw 6, 36(1)
+; ASM32-DAG: stw 7, 40(1)
+; ASM32-DAG: stw 8, 44(1)
+; ASM32-DAG: stw 9, 48(1)
+; ASM32-DAG: stw 10, 52(1)
+; ASM32-DAG: blr
+
+
+; CHECK-LABEL: name: int_stack_va_arg
+; CHECK-LABEL: liveins:
+; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r4', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r5', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r6', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r7', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r8', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r9', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r10', virtual-reg: '' }
+
+; CHECK-LABEL: fixedStack:
+; 32BIT: - { id: 0, type: default, offset: 56, size: 4
+; CHECK-LABEL: body: |
+; 32BIT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
+; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r4, killed renamable $r3
+; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r5
+; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6
+; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r7
+; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r8
+; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r9
+; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r10
+; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r11
+; 32BIT-DAG: renamable $r11 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.1, align 8)
+; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $r3
+
+; CHECKASM-LABEL: .int_stack_va_arg:
+; ASM32-DAG: lwz 11, 56(1)
+; ASM32-DAG: add 3, 4, 3
+; ASM32-DAG: add 3, 3, 5
+; ASM32-DAG: add 3, 3, 6
+; ASM32-DAG: add 3, 3, 7
+; ASM32-DAG: add 3, 3, 8
+; ASM32-DAG: add 3, 3, 9
+; ASM32-DAG: add 3, 3, 10
+; ASM32-DAG: add 3, 3, 11
+; ASM32-DAG: blr
+
+; CHECK-LABEL: name: double_va_arg
+; CHECK-LABEL: liveins:
+; 32BIT-NEXT: - { reg: '$f1', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r5', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r6', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r7', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r8', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r9', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r10', virtual-reg: '' }
+
+; CHECK-LABEL: fixedStack:
+; 32BIT: - { id: 0, type: default, offset: 32, size: 4
+; CHECK-LABEL: body: |
+; 32BIT: liveins: $f1, $r5, $r6, $r7, $r8, $r9, $r10
+; 32BIT-DAG: STW renamable $r5, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0, align 16)
+; 32BIT-DAG: STW renamable $r6, 4, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 4)
+; 32BIT-DAG: STW killed renamable $r7, 8, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 8, align 8)
+; 32BIT-DAG: STW killed renamable $r8, 12, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r9, 16, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 16, align 16)
+; 32BIT-DAG: STW killed renamable $r10, 20, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
+; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $f1
+
+; CHECKASM-LABEL: .double_va_arg:
+; ASM32-DAG: stw 5, 32(1)
+; ASM32-DAG: stw 6, 36(1)
+; ASM32-DAG: stw 7, 40(1)
+; ASM32-DAG: stw 8, 44(1)
+; ASM32-DAG: stw 9, 48(1)
+; ASM32-DAG: stw 10, 52(1)
+; ASM32-DAG: fadd 1, 0, 1
+
+; CHECK-LABEL: name: double_stack_va_arg
+; CHECK-LABEL: liveins:
+; 32BIT-NEXT: - { reg: '$f1', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$f2', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$f3', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$f4', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$f5', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$f6', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$f7', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$f8', virtual-reg: '' }
+
+; CHECK-LABEL: fixedStack:
+; 32BIT: - { id: 0, type: default, offset: 88, size: 4
+; CHECK-LABEL: body: |
+; 32BIT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8
+; 32BIT-DAG: renamable $r3 = LWZ 4, %fixed-stack.0 :: (load 4 from %ir.argp.cur10 + 4)
+; 32BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f1, implicit $rm
+; 32BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
+; 32BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f3, implicit $rm
+; 32BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f4, implicit $rm
+; 32BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f5, implicit $rm
+; 32BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f6, implicit $rm
+; 32BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f7, implicit $rm
+; 32BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = nofpexcept FADD killed renamable $f[[SCRATCHREG:[0-9]+]], killed renamable $f8, implicit $rm
+; 32BIT-DAG: STW killed renamable $r3, 4, %stack.1 :: (store 4 into %stack.1 + 4)
+; 32BIT-DAG: renamable $r3 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.argp.cur10, align 8)
+; 32BIT-DAG: STW killed renamable $r3, 0, %stack.1 :: (store 4 into %stack.1, align 8)
+; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $f1
+
+; CHECKASM-LABEL: .double_stack_va_arg:
+; ASM32-DAG: fadd [[SCRATCHREG:[0-9]+]], 1, 2
+; ASM32-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 3
+; ASM32-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 4
+; ASM32-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 5
+; ASM32-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 6
+; ASM32-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 7
+; ASM32-DAG: fadd [[SCRATCHREG:[0-9]+]], [[SCRATCHREG:[0-9]+]], 8
+; ASM32-DAG: fadd 1, [[SCRATCHREG:[0-9]+]], 1
+; ASM32-DAG: lwz [[DBLREG:[0-9]+]], 88(1)
+; ASM32-DAG: lwz [[DBLREG2:[0-9]+]], 92(1)
+; ASM32-DAG: blr
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3238,7 +3238,7 @@
SDLoc dl(Op);
- if (Subtarget.isPPC64()) {
+ if (Subtarget.isPPC64() || Subtarget.isAIXABI()) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
@@ -6987,9 +6987,6 @@
CallConv == CallingConv::Fast) &&
"Unexpected calling convention!");
- if (isVarArg)
- report_fatal_error("This call type is unimplemented on AIX.");
-
if (getTargetMachine().Options.GuaranteedTailCallOpt)
report_fatal_error("Tail call support is unimplemented on AIX.");
@@ -7007,6 +7004,7 @@
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo &MFI = MF.getFrameInfo();
CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
const EVT PtrVT = getPointerTy(MF.getDataLayout());
@@ -7033,7 +7031,7 @@
if (VA.isMemLoc() && VA.needsCustom())
continue;
- if (VA.isRegLoc()) {
+ if (VA.isRegLoc() && !VA.needsCustom()) {
MVT::SimpleValueType SVT = ValVT.getSimpleVT().SimpleTy;
unsigned VReg =
MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
@@ -7046,23 +7044,26 @@
InVals.push_back(ArgValue);
continue;
}
-
- const unsigned LocSize = LocVT.getStoreSize();
- const unsigned ValSize = ValVT.getStoreSize();
- assert((ValSize <= LocSize) && "Object size is larger than size of MemLoc");
- int CurArgOffset = VA.getLocMemOffset();
- // Objects are right-justified because AIX is big-endian.
- if (LocSize > ValSize)
- CurArgOffset += LocSize - ValSize;
- MachineFrameInfo &MFI = MF.getFrameInfo();
- // Potential tail calls could cause overwriting of argument stack slots.
- const bool IsImmutable =
- !(getTargetMachine().Options.GuaranteedTailCallOpt &&
- (CallConv == CallingConv::Fast));
- int FI = MFI.CreateFixedObject(ValSize, CurArgOffset, IsImmutable);
- SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
- SDValue ArgValue = DAG.getLoad(ValVT, dl, Chain, FIN, MachinePointerInfo());
- InVals.push_back(ArgValue);
+ if (VA.isMemLoc()) {
+ const unsigned LocSize = LocVT.getStoreSize();
+ const unsigned ValSize = ValVT.getStoreSize();
+ assert((ValSize <= LocSize) &&
+ "Object size is larger than size of MemLoc");
+ int CurArgOffset = VA.getLocMemOffset();
+ // Objects are right-justified because AIX is big-endian.
+ if (LocSize > ValSize)
+ CurArgOffset += LocSize - ValSize;
+ // Potential tail calls could cause overwriting of argument stack slots.
+ const bool IsImmutable =
+ !(getTargetMachine().Options.GuaranteedTailCallOpt &&
+ (CallConv == CallingConv::Fast));
+ int FI = MFI.CreateFixedObject(ValSize, CurArgOffset, IsImmutable);
+ SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
+ SDValue ArgValue =
+ DAG.getLoad(ValVT, dl, Chain, FIN, MachinePointerInfo());
+ InVals.push_back(ArgValue);
+ continue;
+ }
}
// On AIX a minimum of 8 words is saved to the parameter save area.
@@ -7080,6 +7081,43 @@
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
FuncInfo->setMinReservedArea(CallerReservedArea);
+ SmallVector<SDValue, 8> MemOps;
+
+ if (isVarArg) {
+ FuncInfo->setVarArgsFrameIndex(
+ MFI.CreateFixedObject(PtrByteSize, CCInfo.getNextStackOffset(), true));
+ SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
+
+ static const MCPhysReg Gpr_32[] = {PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+ PPC::R7, PPC::R8, PPC::R9, PPC::R10};
+
+ static const MCPhysReg Gpr_64[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6,
+ PPC::X7, PPC::X8, PPC::X9, PPC::X10};
+ const unsigned NumGPArgRegs = array_lengthof(IsPPC64 ? Gpr_64 : Gpr_32);
+
+ // The fixed integer arguments of a variadic function are stored to the
+ // VarArgsFrameIndex on the stack so that they may be loaded by
+ // dereferencing the result of va_next.
+ for (unsigned GPRIndex =
+ (CCInfo.getNextStackOffset() - LinkageSize) / PtrByteSize;
+ GPRIndex < NumGPArgRegs; ++GPRIndex) {
+
+ const unsigned VReg =
+ IsPPC64 ? MF.addLiveIn(Gpr_64[GPRIndex], &PPC::G8RCRegClass)
+ : MF.addLiveIn(Gpr_32[GPRIndex], &PPC::GPRCRegClass);
+
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
+ SDValue Store =
+ DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
+ MemOps.push_back(Store);
+ // Increment the address for the next argument to store.
+ SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
+ FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
+ }
+ }
+ if (!MemOps.empty())
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
+
return Chain;
}
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