Author: Mikhail Maltsev Date: 2020-02-24T12:49:20Z New Revision: 12fed51c0807b0727f9eecdd3dcf774a82fa7ecd
URL: https://github.com/llvm/llvm-project/commit/12fed51c0807b0727f9eecdd3dcf774a82fa7ecd DIFF: https://github.com/llvm/llvm-project/commit/12fed51c0807b0727f9eecdd3dcf774a82fa7ecd.diff LOG: [ARM,MVE] Remove 64-bit variants of vbrsrq* intrinsics Summary: According to the ACLE the vbrsrq* intrinsics don't accept vectors with 64-bit elements (and neither does the corresponding VBRSR instruction). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: simon_tatham Subscribers: kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D75038 Added: Modified: clang/include/clang/Basic/arm_mve.td Removed: ################################################################################ diff --git a/clang/include/clang/Basic/arm_mve.td b/clang/include/clang/Basic/arm_mve.td index ca7246d78bd6..7150852d7004 100644 --- a/clang/include/clang/Basic/arm_mve.td +++ b/clang/include/clang/Basic/arm_mve.td @@ -1310,7 +1310,7 @@ foreach desttype = !listconcat(T.Int16, T.Int32, T.Float) in { } } -let params = T.All in { +let params = T.Usual in { let pnt = PNT_NType in def vbrsrq_n: Intrinsic<Vector, (args Vector:$a, s32:$b), (IRInt<"vbrsr", [Vector]> $a, $b)>; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
