Eugene.Zelenko added inline comments.
================
Comment at: clang-tidy/altera/KernelNameRestrictionCheck.cpp:21
+namespace {
+class KernelNameRestrictionPPCallbacks : public PPCallbacks {
+public:
----------------
Please separate with empty line.
================
Comment at: clang-tidy/altera/KernelNameRestrictionCheck.cpp:46
+};
+} // namespace
+
----------------
Please separate with empty line.
================
Comment at: docs/ReleaseNotes.rst:79
+
+ Checks for cases where the kernel source file is named "kernel.cl",
+ "Verilog.cl", or "VHDL.cl".
----------------
Please fix indentation and use single back-ticks to highlight file names. Same
in documentation.
================
Comment at: docs/clang-tidy/checks/altera-kernel-name-restriction.rst:13
+
+As per the "Guidelines for Naming the Kernel" section in the "Intel FPGA SDK
+for OpenCL Pro Edition: Programming Guide."
----------------
May be link is better?
Repository:
rCTE Clang Tools Extra
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D72218/new/
https://reviews.llvm.org/D72218
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