luismarques added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:36 +// The only physical register that isn't saved is x2 (SP), which is used by the +// processor when the interrupt happens. + ---------------- Nitpick: "the interrupt happens" -> "an interrupt happens" (or, even better, "is serviced"). ================ Comment at: llvm/test/CodeGen/RISCV/calling-conv-ilp32e-double-bug.ll:1 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -target-abi ilp32e -mattr=+f -verify-machineinstrs < %s ---------------- It would be good to describe in a comment what the bug is. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
