ab added inline comments.
================ Comment at: llvm/lib/Target/AArch64/AArch64.td:587 + "Apple A10", [ + ProcAppleA7, + FeatureCRC, ---------------- ab wrote: > t.p.northover wrote: > > ab wrote: > > > I'm not sure we want to reuse the features: > > > - everything will get stuck with FeatureZCZeroingFPWorkaround, right? > > > (but maybe we can remove features in this list? I don't think so) > > > - it probably becomes harder to tune later chips, but that's admittedly a > > > theoretical problem at this point > > > - some of the features can be generation-specific > > Good points. It's a shame to duplicate everything (and solvable by > > splitting uArch stuff from the progressive features), but it does seem to > > be existing practice. > > > > I'll rework it to be more in line with the others and add a test for the > > workaround you mentioned; that should have been spotted. > Hmm, how about having these in plain top-level tablegen lists? That lets you > do `(sub)`, which might be sufficient (I don't think that lets us have these cpu "features" though, but TBH I'm not sure what they achieve anyway) CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70779/new/ https://reviews.llvm.org/D70779 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
