Author: Simon Atanasyan Date: 2019-11-05T12:10:58+03:00 New Revision: e578d0fd295a67bce1e1fc922237f459deb49c7e
URL: https://github.com/llvm/llvm-project/commit/e578d0fd295a67bce1e1fc922237f459deb49c7e DIFF: https://github.com/llvm/llvm-project/commit/e578d0fd295a67bce1e1fc922237f459deb49c7e.diff LOG: [mips] Fix `__mips_isa_rev` macros value for Octeon CPU Added: Modified: clang/lib/Basic/Targets/Mips.cpp clang/test/Preprocessor/init.c Removed: ################################################################################ diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp index 2cafbe87a996..4ca7f08af823 100644 --- a/clang/lib/Basic/Targets/Mips.cpp +++ b/clang/lib/Basic/Targets/Mips.cpp @@ -61,7 +61,7 @@ void MipsTargetInfo::fillValidCPUList( unsigned MipsTargetInfo::getISARev() const { return llvm::StringSwitch<unsigned>(getCPU()) .Cases("mips32", "mips64", 1) - .Cases("mips32r2", "mips64r2", 2) + .Cases("mips32r2", "mips64r2", "octeon", 2) .Cases("mips32r3", "mips64r3", 3) .Cases("mips32r5", "mips64r5", 5) .Cases("mips32r6", "mips64r6", 6) diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c index 18972de35348..4e79077687c7 100644 --- a/clang/test/Preprocessor/init.c +++ b/clang/test/Preprocessor/init.c @@ -4832,6 +4832,15 @@ // MIPS-ARCH-64R6:#define _MIPS_ISA _MIPS_ISA_MIPS64 // MIPS-ARCH-64R6:#define __mips_isa_rev 6 // +// RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \ +// RUN: -target-cpu octeon < /dev/null \ +// RUN: | FileCheck -match-full-lines -check-prefix MIPS-ARCH-OCTEON %s +// +// MIPS-ARCH-OCTEON:#define _MIPS_ARCH "octeon" +// MIPS-ARCH-OCTEON:#define _MIPS_ARCH_OCTEON 1 +// MIPS-ARCH-OCTEON:#define _MIPS_ISA _MIPS_ISA_MIPS64 +// MIPS-ARCH-OCTEON:#define __mips_isa_rev 2 +// // Check MIPS float ABI macros // // RUN: %clang_cc1 -E -dM -ffreestanding \ _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
