[PATCH] D17378: Add additional Hi/Lo registers to Clang MipsTargetInfoBase

[Hrvoje Varga via cfe-commits]

hvarga created this revision.
hvarga added reviewers: hfinkel, atrick, chandlerc.
hvarga added subscribers: cfe-commits, petarj.

This patch fixes bug https://dmz-portal.mips.com/bugz/show_bug.cgi?id=2300 by 
adding additional (missing) Hi/Lo registers to the Clang `MipsTargetInfoBase` 
class.

http://reviews.llvm.org/D17378

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/mips-inline-asm.c

Index: test/CodeGen/mips-inline-asm.c
===================================================================
--- test/CodeGen/mips-inline-asm.c
+++ test/CodeGen/mips-inline-asm.c
@@ -17,3 +17,15 @@
   asm("lw $1, %0" :: "R"(data));
   // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data)
 }
+
+int additionalClobberedRegisters () {
+  int temp0;
+  asm volatile(
+                "mfhi %[temp0], $ac1 \n\t"
+                  : [temp0]"=&r"(temp0)
+                  :
+                  : "memory", "t0", "t1", "$ac1hi", "$ac1lo", "$ac2hi", 
"$ac2lo", "$ac3hi", "$ac3lo"
+  );
+  return 0;
+  // CHECK: call i32 asm sideeffect "mfhi $0, $$ac1 \0A\09", 
"=&r,~{memory},~{$8},~{$9},~{$ac1hi},~{$ac1lo},~{$ac2hi},~{$ac2lo},~{$ac3hi},~{$ac3lo},~{$1}"
+}
Index: lib/Basic/Targets.cpp
===================================================================
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -6678,7 +6678,8 @@
       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
       // Hi/lo and condition register names
       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
-      "$fcc5","$fcc6","$fcc7",
+      "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
+      "$ac3hi","$ac3lo",
       // MSA register names
       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",



Index: test/CodeGen/mips-inline-asm.c
===================================================================
--- test/CodeGen/mips-inline-asm.c
+++ test/CodeGen/mips-inline-asm.c
@@ -17,3 +17,15 @@
   asm("lw $1, %0" :: "R"(data));
   // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data)
 }
+
+int additionalClobberedRegisters () {
+  int temp0;
+  asm volatile(
+                "mfhi %[temp0], $ac1 \n\t"
+                  : [temp0]"=&r"(temp0)
+                  :
+                  : "memory", "t0", "t1", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi", "$ac3lo"
+  );
+  return 0;
+  // CHECK: call i32 asm sideeffect "mfhi $0, $$ac1 \0A\09", "=&r,~{memory},~{$8},~{$9},~{$ac1hi},~{$ac1lo},~{$ac2hi},~{$ac2lo},~{$ac3hi},~{$ac3lo},~{$1}"
+}
Index: lib/Basic/Targets.cpp
===================================================================
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -6678,7 +6678,8 @@
       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
       // Hi/lo and condition register names
       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
-      "$fcc5","$fcc6","$fcc7",
+      "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
+      "$ac3hi","$ac3lo",
       // MSA register names
       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",

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