[PATCH] D66266: [WIP][RISCV] Set MaxAtomicPromoteWidth and MaxAtomicInlineWidth

[Pengxuan Zheng via Phabricator via cfe-commits]

pzheng created this revision.
Herald added subscribers: cfe-commits, s.egerton, lenary, Jim, benna, psnobl, 
jocewei, PkmX, jfb, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, 
apazos, simoncook, johnrusso, rbar, asb.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D66266

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/atomic-ops-riscv.c


Index: clang/test/CodeGen/atomic-ops-riscv.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/atomic-ops-riscv.c
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple=riscv32 | FileCheck %s
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple=riscv64 | FileCheck %s
+// REQUIRES: riscv-registered-target
+
+#ifndef ALREADY_INCLUDED
+#define ALREADY_INCLUDED
+
+#include <stdatomic.h>
+
+// Note: this test is based off atomic-ops.c.
+// TODO: Add more tests.
+//
+// Basic IRGen tests for __c11_atomic_* and GNU __atomic_*
+
+int fi1(_Atomic(int) *i) {
+  // CHECK-LABEL: @fi1
+  // CHECK: load atomic i32, i32* {{.*}} seq_cst
+  return __c11_atomic_load(i, memory_order_seq_cst);
+}
+
+int fi1a(int *i) {
+  // CHECK-LABEL: @fi1a
+  // CHECK: load atomic i32, i32* {{.*}} seq_cst
+  int v;
+  __atomic_load(i, &v, memory_order_seq_cst);
+  return v;
+}
+
+int fi1b(int *i) {
+  // CHECK-LABEL: @fi1b
+  // CHECK: load atomic i32, i32* {{.*}} seq_cst
+  return __atomic_load_n(i, memory_order_seq_cst);
+}
+
+#endif
Index: clang/lib/Basic/Targets/RISCV.h
===================================================================
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -23,6 +23,8 @@
 
 // RISC-V Target
 class RISCVTargetInfo : public TargetInfo {
+  void setAtomic();
+
 protected:
   std::string ABI;
   bool HasM;
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -131,6 +131,13 @@
       .Default(false);
 }
 
+void RISCVTargetInfo::setAtomic() {
+  bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
+
+  MaxAtomicPromoteWidth = Is64Bit ? 64 : 32;
+  MaxAtomicInlineWidth = Is64Bit ? 64 : 32;
+}
+
 /// Perform initialization based on the user configured set of features.
 bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
                                            DiagnosticsEngine &Diags) {
@@ -147,5 +154,7 @@
       HasC = true;
   }
 
+  setAtomic();
+
   return true;
 }



Index: clang/test/CodeGen/atomic-ops-riscv.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/atomic-ops-riscv.c
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple=riscv32 | FileCheck %s
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple=riscv64 | FileCheck %s
+// REQUIRES: riscv-registered-target
+
+#ifndef ALREADY_INCLUDED
+#define ALREADY_INCLUDED
+
+#include <stdatomic.h>
+
+// Note: this test is based off atomic-ops.c.
+// TODO: Add more tests.
+//
+// Basic IRGen tests for __c11_atomic_* and GNU __atomic_*
+
+int fi1(_Atomic(int) *i) {
+  // CHECK-LABEL: @fi1
+  // CHECK: load atomic i32, i32* {{.*}} seq_cst
+  return __c11_atomic_load(i, memory_order_seq_cst);
+}
+
+int fi1a(int *i) {
+  // CHECK-LABEL: @fi1a
+  // CHECK: load atomic i32, i32* {{.*}} seq_cst
+  int v;
+  __atomic_load(i, &v, memory_order_seq_cst);
+  return v;
+}
+
+int fi1b(int *i) {
+  // CHECK-LABEL: @fi1b
+  // CHECK: load atomic i32, i32* {{.*}} seq_cst
+  return __atomic_load_n(i, memory_order_seq_cst);
+}
+
+#endif
Index: clang/lib/Basic/Targets/RISCV.h
===================================================================
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -23,6 +23,8 @@
 
 // RISC-V Target
 class RISCVTargetInfo : public TargetInfo {
+  void setAtomic();
+
 protected:
   std::string ABI;
   bool HasM;
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -131,6 +131,13 @@
       .Default(false);
 }
 
+void RISCVTargetInfo::setAtomic() {
+  bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
+
+  MaxAtomicPromoteWidth = Is64Bit ? 64 : 32;
+  MaxAtomicInlineWidth = Is64Bit ? 64 : 32;
+}
+
 /// Perform initialization based on the user configured set of features.
 bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
                                            DiagnosticsEngine &Diags) {
@@ -147,5 +154,7 @@
       HasC = true;
   }
 
+  setAtomic();
+
   return true;
 }

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