[PATCH] D57210: [AArch64] Make the test for rsr and rsr64 stricter

[Petr Hosek via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL352156: [AArch64] Make the test for rsr and rsr64 stricter 
(authored by phosek, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D57210?vs=183448&id=183471#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57210/new/

https://reviews.llvm.org/D57210

Files:
  cfe/trunk/test/CodeGen/builtins-arm64.c


Index: cfe/trunk/test/CodeGen/builtins-arm64.c
===================================================================
--- cfe/trunk/test/CodeGen/builtins-arm64.c
+++ cfe/trunk/test/CodeGen/builtins-arm64.c
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm 
-o - %s | opt -S -mem2reg | FileCheck %s
+#include <stdint.h>
 
 void f0(void *a, void *b) {
        __clear_cache(a,b);
@@ -49,13 +50,17 @@
 // CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 3, i32 0)
 }
 
-unsigned rsr() {
+__typeof__(__builtin_arm_rsr("1:2:3:4:5")) rsr(void);
+
+uint32_t rsr() {
   // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_register.i64(metadata 
![[M0:[0-9]]])
   // CHECK-NEXT: trunc i64 [[V0]] to i32
   return __builtin_arm_rsr("1:2:3:4:5");
 }
 
-unsigned long rsr64() {
+__typeof__(__builtin_arm_rsr64("1:2:3:4:5")) rsr64(void);
+
+uint64_t rsr64() {
   // CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
   return __builtin_arm_rsr64("1:2:3:4:5");
 }



Index: cfe/trunk/test/CodeGen/builtins-arm64.c
===================================================================
--- cfe/trunk/test/CodeGen/builtins-arm64.c
+++ cfe/trunk/test/CodeGen/builtins-arm64.c
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+#include <stdint.h>
 
 void f0(void *a, void *b) {
 	__clear_cache(a,b);
@@ -49,13 +50,17 @@
 // CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 3, i32 0)
 }
 
-unsigned rsr() {
+__typeof__(__builtin_arm_rsr("1:2:3:4:5")) rsr(void);
+
+uint32_t rsr() {
   // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
   // CHECK-NEXT: trunc i64 [[V0]] to i32
   return __builtin_arm_rsr("1:2:3:4:5");
 }
 
-unsigned long rsr64() {
+__typeof__(__builtin_arm_rsr64("1:2:3:4:5")) rsr64(void);
+
+uint64_t rsr64() {
   // CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
   return __builtin_arm_rsr64("1:2:3:4:5");
 }

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