Octeon 2 does not have MSA. Octeon 2 does not have any SIMD extensions implemented. Octeon 2 does not even have a floating point unit. MSA is newer than MIPS64r2/3.
Thanks, Andrew On Sat, Oct 20, 2018, 5:51 AM Jeffrey Walton via cfarm-users < cfarm-users@lists.tetaneutral.net> wrote: > Hi Everyone, > > https://cfarm.tetaneutral.net/machines/list/ says GCC22 to GCC24 is > mips64. The cpuinfo is below from GCC23. I can't tell if this machine > has MIPS SIMD Architecture (MSA) extensions. > > I know the Cavium Octeon II/CN6120 should lead me to a spec sheet but > I am having trouble finding the information. I think the mips64r2 > implies MSA but I could be mistaken. > > Does the Octeon II/CN6120 have MSA? If not, then what should I be > looking for when reading through marketing material and technical > descriptions? > > Thanks > > +++++++++++ > $ cat /proc/cpuinfo > system type : UBNT_E200 (CN6120p1.1-1000-NSP) > machine : Unknown > processor : 0 > cpu model : Cavium Octeon II V0.1 > BogoMIPS : 2000.00 > wait instruction : yes > microsecond timers : yes > tlb_entries : 128 > extra interrupt vector : yes > hardware watchpoint : yes, count: 2, address/irw mask: [0x0ffc, 0x0ffb] > isa : mips1 mips2 mips3 mips4 mips5 mips64r2 > ASEs implemented : > shadow register sets : 1 > kscratch registers : 3 > core : 0 > VCED exceptions : not available > VCEI exceptions : not available > > processor : 1 > cpu model : Cavium Octeon II V0.1 > BogoMIPS : 2000.00 > wait instruction : yes > microsecond timers : yes > tlb_entries : 128 > extra interrupt vector : yes > hardware watchpoint : yes, count: 2, address/irw mask: [0x0ffc, 0x0ffb] > isa : mips1 mips2 mips3 mips4 mips5 mips64r2 > ASEs implemented : > shadow register sets : 1 > kscratch registers : 3 > core : 1 > VCED exceptions : not available > VCEI exceptions : not available > _______________________________________________ > cfarm-users mailing list > cfarm-users@lists.tetaneutral.net > https://lists.tetaneutral.net/listinfo/cfarm-users >
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