> On 17 Mar, 2021, at 12:04 am, Dave Taht <[email protected]> wrote: > > Is that based on measurements?
Yes, Pete did some. > I did not care for the pi3's behavior much. Unlike the Pi 3, the Pi 4 has a true GigE MAC built into the SoC, and the USB3 controller has enough throughput to actually support a second GigE port; it's attached to a real PCIe lane. This means it can move packets from one to the other, in both directions at once, at wire speed without relying on an offload engine (which it doesn't have). That's perfect for SQM. In older Pis, the Ethernet port was attached over USB2. That doesn't have enough throughput to support GigE, and most models had a 100base-TX port as a consequence. There's a similar bottleneck in most CPE routers between the CPU and the Ethernet hardware complex, with the offload engine being part of the latter. That bottleneck is why SQM can't reach wire speed on that class of hardware. - Jonathan Morton _______________________________________________ Cerowrt-devel mailing list [email protected] https://lists.bufferbloat.net/listinfo/cerowrt-devel
