Hi, I don't know if it's the same on Sifive based CPU's but on the D1 (doesn't boot beyond main() yet) the FS bits are set. These are floating point indicators, and I thought these should be off? In my debugs I have found this:
1000000000000000000000000000001000000000000000000110000100000000 p 8000000200006100 that is the respective binary and hex register that the CSR gave on my D1. I have turned this off in locore.S by unsetting the bits in CSR. it's just 2 instructions more. Please have a look in page 39 of this RISCV-privileged (2021) document: https://mainrechner.de/riscv-privileged-20211203.pdf It is the same bit offset in mstatus and sstatus. On the D1 after the CPU is reset the FP bits go back to 0, meaning that on its depressive boot-life the FS bits have been turned on. to check this I would add a debugging printf high in pmap_bootstrap() that looks like so: status = csr_read(sstatus); printf("sstatus: %lX\n", status); Principally I can do this too but it would take me some time changing source trees and recompiling. To turn floating point off, I have set this in locore.S: /* turn off any possible FP bits set */ li t0, SSTATUS_FS_MASK csrc sstatus, t0 under the pagetable END. Best Regards, -peter PS: If you would like me to keep D1 stuff to myself without relaying findings back to you let me know. I know we don't use floating point code in the kernel whatsoever. Am I wrong? -- Over thirty years experience on Unix-like Operating Systems starting with QNX.
