The GNU make 3.82 manual reads:
Normally, this is exactly what you want: if a target's prerequisite
is updated, then the target should also be updated.
Occasionally, however, you have a situation where you want to impose
a specific ordering on the rules to be invoked without forcing the
target to be updated if one of those rules is executed.
But if I write a makefile like this:
ALL = a b c d
default:
echo Specify a target: $(ALL); exit 1
.PHONY: $(ALL)
$(ALL):
@echo $@
a: | b
b: | c
c: | d
then I get:
$ make a # Not what I expected, but what actually happened.
d
c
b
a
which is not what I'd have expected reading the documentation above; what
I would have expected was that "a" alone would be run:
$ make a # What I expected, but did not happen.
a
OTOH, if I had invoked more than one prerequisite at the same time, I'd
have expected the ordering among them to be respected, like this:
$ make b a c # What would I expected.
c
b
a
Is this a bug in make, in its documentation, or it's just me
misunderstanding something?
Regards,
Stefano
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