On Tue, 2010-09-28 at 13:54 +0400, Alexander Kornilov wrote:
> BUG #0001:
> -----------
>
> Description: The rule for generation dependency file (%.d) doesn't work
> on Linux platform;
> Severity: Major;
>
> Steps to reproduce:
> 1. Unpack bug_0001.zip files from letter attachment;
> 2. Execute makefile from archive on Linux platform. Result of operation:
> > make
> Creating dir Obj
> Generate dependency for test1.cpp
> Generate dependency for test2.cpp
Interesting. When I tried your test case with GNU make 3.82 it failed
with a different, very subtle bug.
However, your makefile is wrong and that's why it's failing for you in
GNU make 3.81. I have no idea why it works in Windows; if it does
that's a bug in the Windows version of make, IMO.
You have rules like this:
%.o: %.cpp makefile
@echo Compiling $<;
@echo $@ >$(objDir)$(slash)$@
This goes against one of the fundamental rules of writing makefiles:
your recipe MUST update the target that make wants it to. The target
make wants it to update is the file $...@. Your recipe is not creating $@,
it's creating $(objDir)$(slash)$@, which is an entirely different file.
Basically, your approach is not going to work. You are trying to use
vpath to find _OBJECT_ files, but when make runs the object files don't
yet exist so make can't find them. You can't use vpath for this; vpath
is only for finding _SOURCE_ files: files that always exist, not files
that make builds.
I think you should read the following; they bear directly on your
situation:
http://make.mad-scientist.us/rules.html
http://make.mad-scientist.us/vpath.html
http://make.mad-scientist.us/autodep.html
> Klocwork:
> ----------
>
> In file klocwork_report_make_v3.82.zip I attach static code analysis
> tool Klocwork report for make v3.82 generated by my build system.
> Klocwork find many vulnerabilities and warnings in make code. According
> my experience Klocwork is 'smart' tool and maybe you find it's comments
> useful for make improvement.
I'll take a look but often these tools show many false positives.
> Make language:
> ---------------
> In my build system I am often use condition constructions and upset by
> make language restrictions Are you plan support condition construction
> like this:
> ifeq ($(SHELL), sh.exe) && (($(target_platform), WinXP) ||
> ($(target_platform), WinVista))
> endif
>
> ifeq ($(SHELL), sh.exe)
> <..>
> elif ($(SHELL), /bin/bash)
> <..>
> endif
>
> I mind AND (&& and OR (||) 'elif' operations in ifeq.
In GNU make 3.82 you can write "ifeq else ifeq endif"-style constructs.
There are also $(and ...) and $(or ...) functions available in both 3.81
and 3.82. However, they don't work quite as you describe above.
Please check the manual for full details.
> Questions:
> -----------
>
> I doesn't find solve of this my problem in user-guide. Could I 'know'
> what particular target user pass to make?
> e.g. > make clean
Look up the MAKECMDGOALS variable in the manual.
--
-------------------------------------------------------------------------------
Paul D. Smith <psm...@gnu.org> Find some GNU make tips at:
http://www.gnu.org http://make.mad-scientist.net
"Please remain calm...I may be mad, but I am a professional." --Mad Scientist
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