---
i386/i386/locore.S | 15 +++++++++++++++
i386/i386/pic.h | 4 +++-
i386/i386at/idt.h | 17 +++++++++++------
i386/i386at/int_init.c | 15 +++++++++++++--
4 files changed, 42 insertions(+), 9 deletions(-)
diff --git a/i386/i386/locore.S b/i386/i386/locore.S
index bee3630c..8a1054a6 100644
--- a/i386/i386/locore.S
+++ b/i386/i386/locore.S
@@ -607,6 +607,7 @@ ENTRY(call_continuation)
jmp *%eax /* goto continuation */
+/* IOAPIC has 24 interrupts, put spurious in the same array */
#define INTERRUPT(n) \
.data 2 ;\
@@ -621,6 +622,7 @@ ENTRY(call_continuation)
.data 2
DATA(int_entry_table)
.text
+/* Legacy APIC interrupts or PIC interrupts */
INTERRUPT(0)
INTERRUPT(1)
INTERRUPT(2)
@@ -637,6 +639,19 @@ INTERRUPT(12)
INTERRUPT(13)
INTERRUPT(14)
INTERRUPT(15)
+#ifdef APIC
+/* APIC PCI interrupts PIRQ A-H */
+INTERRUPT(16)
+INTERRUPT(17)
+INTERRUPT(18)
+INTERRUPT(19)
+INTERRUPT(20)
+INTERRUPT(21)
+INTERRUPT(22)
+INTERRUPT(23)
+/* Spurious interrupt, set irq number to vect number */
+INTERRUPT(255)
+#endif
/* XXX handle NMI - at least print a warning like Linux does. */
diff --git a/i386/i386/pic.h b/i386/i386/pic.h
index 6434bf08..0ccf1c9a 100644
--- a/i386/i386/pic.h
+++ b/i386/i386/pic.h
@@ -96,7 +96,7 @@ WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#if defined(AT386) || defined(ATX86_64)
-#define PICM_VECTBASE 0x40
+#define PICM_VECTBASE 0x20
#define PICS_VECTBASE PICM_VECTBASE + 0x08
#endif /* defined(AT386) */
@@ -176,6 +176,8 @@ WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
#define READ_IR_ONRD 0x00
#define READ_IS_ONRD 0x01
+#define PIC_MASK_ZERO 0x00
+
#ifndef __ASSEMBLER__
extern void picinit (void);
extern int curr_pic_mask;
diff --git a/i386/i386at/idt.h b/i386/i386at/idt.h
index 56e6296c..ac065aef 100644
--- a/i386/i386at/idt.h
+++ b/i386/i386at/idt.h
@@ -24,13 +24,18 @@
#ifndef _I386AT_IDT_
#define _I386AT_IDT_
-/* On a standard PC, we only need 16 interrupt vectors,
- because that's all the PIC hardware supports. */
-/* XX But for some reason we program the PIC
- to use vectors 0x40-0x4f rather than 0x20-0x2f. Fix. */
-#define IDTSZ (0x20+0x20+0x10)
+/* There are 256 interrupt vectors on x86,
+ * the first 32 are taken by cpu faults */
+#define IDTSZ (0x100)
-#define PIC_INT_BASE 0x40
+/* PIC sits at 0x20-0x2f */
+#define PIC_INT_BASE 0x20
+
+/* IOAPIC sits at 0x30-0x47 */
+#define IOAPIC_INT_BASE 0x30
+
+/* IOAPIC spurious interrupt vector set to 0xff */
+#define IOAPIC_SPURIOUS_BASE 0xff
#include <i386/idt-gen.h>
diff --git a/i386/i386at/int_init.c b/i386/i386at/int_init.c
index 43daad8b..6da627dd 100644
--- a/i386/i386at/int_init.c
+++ b/i386/i386at/int_init.c
@@ -30,10 +30,21 @@ extern vm_offset_t int_entry_table[];
void int_init(void)
{
int i;
-
- for (i = 0; i < 16; i++)
+#ifndef APIC
+ for (i = 0; i < 16; i++) {
fill_idt_gate(PIC_INT_BASE + i,
int_entry_table[i], KERNEL_CS,
ACC_PL_K|ACC_INTR_GATE, 0);
+ }
+#else
+ for (i = 0; i < 24; i++) {
+ fill_idt_gate(IOAPIC_INT_BASE + i,
+ int_entry_table[i], KERNEL_CS,
+ ACC_PL_K|ACC_INTR_GATE, 0);
+ }
+ fill_idt_gate(IOAPIC_SPURIOUS_BASE,
+ int_entry_table[24], KERNEL_CS,
+ ACC_PL_K|ACC_INTR_GATE, 0);
+#endif
}
--
2.30.1
