https://sourceware.org/bugzilla/show_bug.cgi?id=33893
--- Comment #9 from Zheng Bao <fishbaoz at hotmail dot com> --- (In reply to H.J. Lu from comment #8) > (In reply to Craaijo, Jos from comment #0) > > The instruction 66F30FD6E4 is decoded incorrectly by libopcodes. It is > > decoded as: > > > > movq2dq %xmm4,%xmm4 > > > > but it should be decoded as: > > > > movq2dq %mm4,%xmm4 > > > > Note the register difference in the first operand. > > > > I suspect the 66 prefix is somehow given priority over the F2/F3 prefixes, > > as this decoding would be correct if the instruction was 660FD6E4. When both > > an F2/F3 and a 66 prefix are present, priority should be given to the F2/F3 > > prefixes. I have checked this behavior against both Intel and AMD CPUs, as > > well as Capstone, XED and Zydis. Unfortunately, I could not find a > > What do Intel/AMD CPUs do? Please refer the test in comment 3. -- You are receiving this mail because: You are on the CC list for the bug.
