Package: binutils-common
Version: 2.44-2
Severity: minor
Tags: patch
* What led up to the situation?
Checking for defects with a new version
test-[g|n]roff -mandoc -t -K utf8 -rF0 -rHY=0 -rCHECKSTYLE=10 -ww -z < "man
page"
[Use "groff -e ' $' -e '\\~$' <file>" to find obvious trailing spaces.]
["test-groff" is a script in the repository for "groff"; is not shipped]
(local copy and "troff" slightly changed by me).
[The fate of "test-nroff" was decided in groff bug #55941.]
* What was the outcome of this action?
Output from "test-groff -mandoc -t -K utf8 -rF0 -rHY=0 -rCHECKSTYLE=10 -ww -z
":
[Reduced output:]
an.tmac:<stdin>:68: style: 1 leading space(s) on input line
[...]
an.tmac:<stdin>:110: style: 3 leading space(s) on input line
[...]
an.tmac:<stdin>:297: style: 4 leading space(s) on input line
[...]
troff:<stdin>:407: warning: font name 'CW' is deprecated
[...]
an.tmac:<stdin>:527: style: use of deprecated macro: .PD
[...]
troff:<stdin>:1317: warning: trailing space in the line
[...]
* What outcome did you expect instead?
No output (no warnings).
-.-
General remarks and further material, if a diff-file exist, are in the
attachments.
-- System Information:
Debian Release: trixie/sid
APT prefers testing
APT policy: (500, 'testing')
Architecture: amd64 (x86_64)
Kernel: Linux 6.12.12-amd64 (SMP w/2 CPU threads; PREEMPT)
Locale: LANG=is_IS.iso88591, LC_CTYPE=is_IS.iso88591 (charmap=ISO-8859-1),
LANGUAGE not set
Shell: /bin/sh linked to /usr/bin/dash
Init: sysvinit (via /sbin/init)
-- no debconf information
Input file is as.1
Output from "mandoc -T lint as.1": (shortened list)
1 empty block: RS
1 input text line longer than 80 bytes: (VR) operands and ve...
[...]
1 whitespace at end of input line
Remove trailing space with: sed -e 's/ *$//'
-.-.
Output from "test-groff -mandoc -t -ww -z as.1": (shortened list)
1 font name 'CW' is deprecated
1 trailing space in the line
Remove trailing space with: sed -e 's/ *$//'
-.-.
Show if Pod::Man generated this.
Who is actually creating this man page? Debian or upstream?
Is the generating software out of date?
2:.\" Automatically generated by Pod::Man 5.0102 (Pod::Simple 3.45)
-.-.
Remove space characters (whitespace) at the end of lines.
Use "git apply ... --whitespace=fix" to fix extra space issues, or use
global configuration "core.whitespace".
Number of lines affected is
1
-.-.
Change '-' (\-) to '\(en' (en-dash) for a (numeric) range.
GNU gnulib has recently (2023-06-18) updated its
"build_aux/update-copyright" to recognize "\(en" in man pages.
as.1:3093:Copyright (c) 1991\-2025 Free Software Foundation, Inc.
-.-.
Remove space in the first column, if not indented.
Use ".in +<number>n" and ".in" to end it; ".nf" and ".fi" to end
it, for an extra indention.
[List of affected lines removed.]
-.-.
Find a repeated word
! 886 --> then
! 1826 --> generate
-.-.
Strings longer than 3/4 of a standard line length (80)
Use "\:" to split the string at the end of an output line, for example a
long URL (web address)
122
[\fB\-mA6\fR|\fB\-mARC600\fR|\fB\-mARC601\fR|\fB\-mA7\fR|\fB\-mARC700\fR|\fB\-mEM\fR|\fB\-mHS\fR]
193 [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]
194 [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]
204 [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
211
[\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR|\fB\-mm9s12x\fR|\fB\-mm9s12xg\fR]
296
[\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|\fB\-m403\fR|\fB\-m405\fR|
297
\fB\-m440\fR|\fB\-m464\fR|\fB\-m476\fR|\fB\-m7400\fR|\fB\-m7410\fR|\fB\-m7450\fR|\fB\-m7455\fR|\fB\-m750cl\fR|\fB\-mgekko\fR|
298
\fB\-mbroadway\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-me500\fR|\fB\-e500x2\fR|\fB\-me500mc\fR|\fB\-me500mc64\fR|\fB\-me5500\fR|
299
\fB\-me6500\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|\fB\-mpower4\fR|\fB\-mpwr4\fR|\fB\-mpower5\fR|\fB\-mpwr5\fR|\fB\-mpwr5x\fR|
300
\fB\-mpower6\fR|\fB\-mpwr6\fR|\fB\-mpower7\fR|\fB\-mpwr7\fR|\fB\-mpower8\fR|\fB\-mpwr8\fR|\fB\-mpower9\fR|\fB\-mpwr9\fR\fB\-ma2\fR|
301
\fB\-mcell\fR|\fB\-mspe\fR|\fB\-mspe2\fR|\fB\-mtitan\fR|\fB\-me300\fR|\fB\-mcom\fR]
305
[\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-le\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR|\fB\-be\fR]
345 [\fB\-SCORE5\fR][\fB\-SCORE5U\fR][\fB\-SCORE7\fR][\fB\-SCORE3\fR]
350
[\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Aleon\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
351
\fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av8plusb\fR|\fB\-Av8plusc\fR|\fB\-Av8plusd\fR
352
\fB\-Av8plusv\fR|\fB\-Av8plusm\fR|\fB\-Av9\fR|\fB\-Av9a\fR|\fB\-Av9b\fR|\fB\-Av9c\fR
353
\fB\-Av9d\fR|\fB\-Av9e\fR|\fB\-Av9v\fR|\fB\-Av9m\fR|\fB\-Asparc\fR|\fB\-Asparcvis\fR
354
\fB\-Asparcvis2\fR|\fB\-Asparcfmaf\fR|\fB\-Asparcima\fR|\fB\-Asparcvis3\fR
356
[\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR]|\fB\-xarch=v8plusb\fR|\fB\-xarch=v8plusc\fR
357
\fB\-xarch=v8plusd\fR|\fB\-xarch=v8plusv\fR|\fB\-xarch=v8plusm\fR|\fB\-xarch=v9\fR
358
\fB\-xarch=v9a\fR|\fB\-xarch=v9b\fR|\fB\-xarch=v9c\fR|\fB\-xarch=v9d\fR|\fB\-xarch=v9e\fR
359
\fB\-xarch=v9v\fR|\fB\-xarch=v9m\fR|\fB\-xarch=sparc\fR|\fB\-xarch=sparcvis\fR
360 \fB\-xarch=sparcvis2\fR|\fB\-xarch=sparcfmaf\fR|\fB\-xarch=sparcima\fR
361 \fB\-xarch=sparcvis3\fR|\fB\-xarch=sparcvisr\fR|\fB\-xarch=sparc5\fR
364 [\fB\-\-enforce\-aligned\-data\fR][\fB\-\-dcti\-couples\-detect\fR]
833 .IP \fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
889 .IP \fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
1009 .IP \fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
1012 .IP \fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
1754 .IP \fB\-malign\-branch=\fR\fITYPE\fR\fB[+\fR\fITYPE\fR\fB...]\fR 4
3041 .IP
\fB\-march=\fR\fICPU\fR\fB[\-\fR\fIEXT\fR\fB...][+\fR\fIEXT\fR\fB...]\fR 4
-.-.
Add a "\&" (or a comma (Oxford comma)) after "e.g." and "i.e.",
or use English words
(man-pages(7)).
Abbreviation points should be marked as such and protected against being
interpreted as an end of sentence, if they are not, and that independent
of the current place on the line.
949:numbered processor names (e.g. 21064) enable the processor-specific PALcode
950:instructions, while the "electro-vlasic" names (e.g. \f(CW\*(C`ev4\*(C'\fR)
do not.
1549:restriction, i.e. despite these otherwise being "enabling" options, using
-.-.
Wrong distance between sentences in the input file.
Separate the sentences and subordinate clauses; each begins on a new
line. See man-pages(7) ("Conventions for source file layout") and
"info groff" ("Input Conventions").
The best procedure is to always start a new sentence on a new line,
at least, if you are typing on a computer.
Remember coding: Only one command ("sentence") on each (logical) line.
E-mail: Easier to quote exactly the relevant lines.
Generally: Easier to edit the sentence.
Patches: Less unaffected text.
Search for two adjacent words is easier, when they belong to the same line,
and the same phrase.
The amount of space between sentences in the output can then be
controlled with the ".ss" request.
Mark a final abbreviation point as such by suffixing it with "\&".
Some sentences (etc.) do not begin on a new line.
Split (sometimes) lines after a punctuation mark; before a conjunction.
Lines with only one (or two) space(s) between sentences could be split,
so latter sentences begin on a new line.
Use
#!/usr/bin/sh
sed -e '/^\./n' \
-e 's/\([[:alpha:]]\)\. */\1.\n/g' $1
to split lines after a sentence period.
Check result with the difference between the formatted outputs.
See also the attachment "general.bugs"
[List of affected lines removed.]
-.-.
Split lines longer than 80 characters into two or more lines.
Appropriate break points are the end of a sentence and a subordinate
clause; after punctuation marks.
Add "\:" to split the string for the output, "\<newline>" in the source.
[List of affected lines removed.]
-.-.
Do not use more than two space characters between sentences or (better)
only a new line character.
2998:expense in code size. This optimization is enabled by default. Note
3004:across a greater range of addresses. This option should be used when
call
3024:across a greater range of addresses. This option should be used when
jump targets can
-.-.
Remove unnecessary double font change (e.g., \fR\fI) in a row or (better)
use a two-fonts macro.
[List with affected line removed.]
-.-
Add a zero (0) in front of a decimal fraction that begins with a period
(.)
7:.if t .sp .5v
-.-.
Put a parenthetical sentence, phrase on a separate line,
if not part of a code.
See man-pages(7), item "semantic newline".
[List of affected lines removed.]
-.-
Use a hyphen between a number and the unit (name) "bit",
see "man-pages(7)", item "Terms to avoid".
1293:Specifies that the both 32 and 16 bit instructions are allowed. This is
the
1297:Restricts the permitted instructions to just the 16 bit set.
1613:AVX instructions with 128bit vector length, which is the default.
1615:with 256bit vector length.
1643:EVEX instructions with 128bit vector length, which is the default.
1645:encode LIG EVEX instructions with 256bit and 512bit vector length,
-.-.
1696:format, which allows more than 32768 sections.
-.-.
Use ".na" (no adjustment) instead of ".ad l" (and ".ad" to begin the
same adjustment again as before).
61:.if n .ad l
-.-.
Add lines to use the CR font for groff instead of CW.
.if t \{\
. ie \\n(.g .ft CR
. el .ft CW
.\}
11:.ft CW
-.-.
Section headings (.SH and .SS) do not need quoting their arguments.
1100:.SS "BPF Options"
3039:.SS "Command-line Options"
3088:.SH "SEE ALSO"
-.-.
\" Define a fallback for font CW with
.if t \{\
. ie \n(.g .ds fC \f(CR
. el .ds fC \f(CW
. \}
. ds fP \fP
.\}
.
.if n \{\
. ds fC \fR
. ds fP \fP
.\}
-.-
Output from "test-groff -mandoc -t -K utf8 -rF0 -rHY=0 -rCHECKSTYLE=10 -ww -z
":
[List of affected lines removed.]
-.-.
Generally:
Split (sometimes) lines after a punctuation mark; before a conjunction.
--- as.1 2025-03-02 22:23:48.097864447 +0000
+++ as.1.new 2025-03-02 23:28:29.153341611 +0000
@@ -3,16 +3,19 @@
.\"
.\" Standard preamble:
.\" ========================================================================
-.de Sp \" Vertical space (when we can't use .PP)
-.if t .sp .5v
+.de Sp\" Vertical space (when we can't use .PP)
+.if t .sp 0.5v
.if n .sp
..
-.de Vb \" Begin verbatim text
-.ft CW
+.de Vb\" Begin verbatim text
+.if t \{\
+. ie \\n(.g .ft CR
+. el .ft CW
+.\}
.nf
.ne \\$1
..
-.de Ve \" End verbatim text
+.de Ve\" End verbatim text
.ft R
.fi
..
@@ -52,18 +55,33 @@
. \}
.\}
.rr rF
+.
+.\" Define a fallback for font CW with
+.if t \{\
+. ie \n(.g .ds fC \f(CR
+. el .ds fC \f(CW
+. \}
+. ds fP \fP
+.\}
+.
+.if n \{\
+. ds fC \fR
+. ds fP \fP
+.\}
+.
.\" ========================================================================
.\"
.IX Title "AS 1"
.TH AS 1 2025-02-19 binutils-2.44 "GNU Development Tools"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
-.if n .ad l
+.if n .na
.nh
.SH NAME
AS \- the portable GNU assembler.
.SH SYNOPSIS
.IX Header "SYNOPSIS"
+.nf
as [\fB\-a\fR[\fBcdghilns\fR][=\fIfile\fR]]
[\fB\-\-alternate\fR]
[\fB\-\-compress\-debug\-sections\fR] [\fB\-\-nocompress\-debug\-sections\fR]
@@ -104,8 +122,10 @@ as [\fB\-a\fR[\fBcdghilns\fR][=\fIfile\f
[\fB\-Z\fR] [\fB@\fR\fIFILE\fR]
[\fItarget-options\fR]
[\fB\-\-\fR|\fIfiles\fR ...]
+.fi
.SH TARGET
.IX Header "TARGET"
+.nf
\&\fITarget AArch64 options:\fR
[\fB\-EB\fR|\fB\-EL\fR]
[\fB\-mabi\fR=\fIABI\fR]
@@ -221,7 +241,7 @@ as [\fB\-a\fR[\fBcdghilns\fR][=\fIfile\f
.PP
\&\fITarget Meta options:\fR
[\fB\-mcpu=\fR\fIcpu\fR] [\fB\-mfpu=\fR\fIcpu\fR] [\fB\-mdsp=\fR\fIcpu\fR]
-\&\fITarget MICROBLAZE options:\fR
+\fITarget MICROBLAZE options:\fR
[\fB\-mlittle\-endian\fR] [\fB\-mbig\-endian\fR]
.PP
\&\fITarget MIPS options:\fR
@@ -394,6 +414,7 @@ as [\fB\-a\fR[\fBcdghilns\fR][=\fIfile\f
[\fB\-sdcc\fR]
[\fB\-fp\-s=\fR\fIFORMAT\fR]
[\fB\-fp\-d=\fR\fIFORMAT\fR]
+.fi
.SH DESCRIPTION
.IX Header "DESCRIPTION"
GNU \fBas\fR is really a family of assemblers.
@@ -404,8 +425,8 @@ including object file formats, most asse
\&\fIpseudo-ops\fR) and assembler syntax.
.PP
\&\fBas\fR is primarily intended to assemble the output of the
-GNU C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker
-\&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR
+GNU C compiler \*(fC\*(C`gcc\*(C'\fR for use by the linker
+\&\*(fC\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR
assemble correctly everything that other assemblers for the same
machine would assemble.
Any exceptions are documented explicitly.
@@ -566,7 +587,7 @@ Define the symbol \fIsym\fR to be \fIval
\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR
indicates a hexadecimal value, and a leading \fB0\fR indicates an octal
value. The value of the symbol can be overridden inside a source file via the
-use of a \f(CW\*(C`.set\*(C'\fR pseudo-op.
+use of a \*(fC\*(C`.set\*(C'\fR pseudo-op.
.IP \fB\-\-dump\-config\fR 4
.IX Item "--dump-config"
Displays how the assembler is configured and then exits.
@@ -577,7 +598,7 @@ Displays how the assembler is configured
.IX Item "--elf-stt-common=yes"
.PD
These options control whether the ELF assembler should generate common
-symbols with the \f(CW\*(C`STT_COMMON\*(C'\fR type. The default can be
controlled
+symbols with the \*(fC\*(C`STT_COMMON\*(C'\fR type. The default can be
controlled
by a configure option \fB\-\-enable\-elf\-stt\-common\fR.
.IP \fB\-\-emulation=\fR\fIname\fR 4
.IX Item "--emulation=name"
@@ -595,8 +616,8 @@ compiler output).
.PD
Generate debugging information for each assembler source line using whichever
debug format is preferred by the target. This currently means either STABS,
-ECOFF or DWARF2. When the debug format is DWARF then a
\f(CW\*(C`.debug_info\*(C'\fR and
-\&\f(CW\*(C`.debug_line\*(C'\fR section is only emitted when the assembly file
doesn't
+ECOFF or DWARF2. When the debug format is DWARF then a
\*(fC\*(C`.debug_info\*(C'\fR and
+\&\*(fC\*(C`.debug_line\*(C'\fR section is only emitted when the assembly file
doesn't
generate one itself.
.IP \fB\-\-gstabs\fR 4
.IX Item "--gstabs"
@@ -683,7 +704,7 @@ Don't suppress informational messages.
Suppress informational messages.
.IP "\fB\-I\fR \fIdir\fR" 4
.IX Item "-I dir"
-Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR
directives.
+Add directory \fIdir\fR to the search list for \*(fC\*(C`.include\*(C'\fR
directives.
.IP \fB\-J\fR 4
.IX Item "-J"
Don't warn about signed overflow.
@@ -753,14 +774,14 @@ both the assembler and the linker.
This option controls whether the assembler should synthesize CFI for
hand-written input. If the input already contains some synthesizable CFI
directives, the assembler ignores them and emits a warning. Note that
-\&\f(CW\*(C`\-\-scfi=experimental\*(C'\fR is not intended to be used for
compiler-generated
+\&\*(fC\*(C`\-\-scfi=experimental\*(C'\fR is not intended to be used for
compiler-generated
code, including inline assembly. This experimental support is work in
progress. Only System V AMD64 ABI is supported.
.Sp
-Each input function in assembly must begin with the \f(CW\*(C`.type\*(C'\fR
directive, and
-should ideally be closed off using a \f(CW\*(C`.size\*(C'\fR directive. When
using SCFI,
-each \f(CW\*(C`.type\*(C'\fR directive prompts GAS to start a new FDE (a.k.a.,
Function
-Descriptor Entry). This implies that with each \f(CW\*(C`.type\*(C'\fR
directive, a
+Each input function in assembly must begin with the \*(fC\*(C`.type\*(C'\fR
directive, and
+should ideally be closed off using a \*(fC\*(C`.size\*(C'\fR directive. When
using SCFI,
+each \*(fC\*(C`.type\*(C'\fR directive prompts GAS to start a new FDE (a.k.a.,
Function
+Descriptor Entry). This implies that with each \*(fC\*(C`.type\*(C'\fR
directive, a
previous block of instructions, if any, is finalised as a distinct FDE.
.IP \fB\-\-sectname\-subst\fR 4
.IX Item "--sectname-subst"
@@ -828,53 +849,53 @@ be marked as being encoded for a little-
.IP \fB\-mabi=\fR\fIabi\fR 4
.IX Item "-mabi=abi"
Specify which ABI the source code uses. The recognized arguments
-are: \f(CW\*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the
generated object
-file in ELF32 and ELF64 format respectively. The default is
\f(CW\*(C`lp64\*(C'\fR.
+are: \*(fC\*(C`ilp32\*(C'\fR and \*(fC\*(C`lp64\*(C'\fR, which decides the
generated object
+file in ELF32 and ELF64 format respectively. The default is
\*(fC\*(C`lp64\*(C'\fR.
.IP \fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
.IX Item "-mcpu=processor[+extension...]"
This option specifies the target processor. The assembler will issue an error
message if an attempt is made to assemble an instruction which will not execute
on the target processor. The following processor names are recognized:
-\&\f(CW\*(C`cortex\-a34\*(C'\fR,
-\&\f(CW\*(C`cortex\-a35\*(C'\fR,
-\&\f(CW\*(C`cortex\-a53\*(C'\fR,
-\&\f(CW\*(C`cortex\-a55\*(C'\fR,
-\&\f(CW\*(C`cortex\-a57\*(C'\fR,
-\&\f(CW\*(C`cortex\-a65\*(C'\fR,
-\&\f(CW\*(C`cortex\-a65ae\*(C'\fR,
-\&\f(CW\*(C`cortex\-a72\*(C'\fR,
-\&\f(CW\*(C`cortex\-a73\*(C'\fR,
-\&\f(CW\*(C`cortex\-a75\*(C'\fR,
-\&\f(CW\*(C`cortex\-a76\*(C'\fR,
-\&\f(CW\*(C`cortex\-a76ae\*(C'\fR,
-\&\f(CW\*(C`cortex\-a77\*(C'\fR,
-\&\f(CW\*(C`cortex\-a78\*(C'\fR,
-\&\f(CW\*(C`cortex\-a78ae\*(C'\fR,
-\&\f(CW\*(C`cortex\-a78c\*(C'\fR,
-\&\f(CW\*(C`cortex\-a510\*(C'\fR,
-\&\f(CW\*(C`cortex\-a520\*(C'\fR,
-\&\f(CW\*(C`cortex\-a710\*(C'\fR,
-\&\f(CW\*(C`cortex\-a720\*(C'\fR,
-\&\f(CW\*(C`ares\*(C'\fR,
-\&\f(CW\*(C`exynos\-m1\*(C'\fR,
-\&\f(CW\*(C`falkor\*(C'\fR,
-\&\f(CW\*(C`neoverse\-n1\*(C'\fR,
-\&\f(CW\*(C`neoverse\-n2\*(C'\fR,
-\&\f(CW\*(C`neoverse\-e1\*(C'\fR,
-\&\f(CW\*(C`neoverse\-v1\*(C'\fR,
-\&\f(CW\*(C`qdf24xx\*(C'\fR,
-\&\f(CW\*(C`saphira\*(C'\fR,
-\&\f(CW\*(C`thunderx\*(C'\fR,
-\&\f(CW\*(C`vulcan\*(C'\fR,
-\&\f(CW\*(C`xgene1\*(C'\fR
-\&\f(CW\*(C`xgene2\*(C'\fR,
-\&\f(CW\*(C`cortex\-r82\*(C'\fR,
-\&\f(CW\*(C`cortex\-x1\*(C'\fR,
-\&\f(CW\*(C`cortex\-x2\*(C'\fR,
-\&\f(CW\*(C`cortex\-x3\*(C'\fR,
+\&\*(fC\*(C`cortex\-a34\*(C'\fR,
+\&\*(fC\*(C`cortex\-a35\*(C'\fR,
+\&\*(fC\*(C`cortex\-a53\*(C'\fR,
+\&\*(fC\*(C`cortex\-a55\*(C'\fR,
+\&\*(fC\*(C`cortex\-a57\*(C'\fR,
+\&\*(fC\*(C`cortex\-a65\*(C'\fR,
+\&\*(fC\*(C`cortex\-a65ae\*(C'\fR,
+\&\*(fC\*(C`cortex\-a72\*(C'\fR,
+\&\*(fC\*(C`cortex\-a73\*(C'\fR,
+\&\*(fC\*(C`cortex\-a75\*(C'\fR,
+\&\*(fC\*(C`cortex\-a76\*(C'\fR,
+\&\*(fC\*(C`cortex\-a76ae\*(C'\fR,
+\&\*(fC\*(C`cortex\-a77\*(C'\fR,
+\&\*(fC\*(C`cortex\-a78\*(C'\fR,
+\&\*(fC\*(C`cortex\-a78ae\*(C'\fR,
+\&\*(fC\*(C`cortex\-a78c\*(C'\fR,
+\&\*(fC\*(C`cortex\-a510\*(C'\fR,
+\&\*(fC\*(C`cortex\-a520\*(C'\fR,
+\&\*(fC\*(C`cortex\-a710\*(C'\fR,
+\&\*(fC\*(C`cortex\-a720\*(C'\fR,
+\&\*(fC\*(C`ares\*(C'\fR,
+\&\*(fC\*(C`exynos\-m1\*(C'\fR,
+\&\*(fC\*(C`falkor\*(C'\fR,
+\&\*(fC\*(C`neoverse\-n1\*(C'\fR,
+\&\*(fC\*(C`neoverse\-n2\*(C'\fR,
+\&\*(fC\*(C`neoverse\-e1\*(C'\fR,
+\&\*(fC\*(C`neoverse\-v1\*(C'\fR,
+\&\*(fC\*(C`qdf24xx\*(C'\fR,
+\&\*(fC\*(C`saphira\*(C'\fR,
+\&\*(fC\*(C`thunderx\*(C'\fR,
+\&\*(fC\*(C`vulcan\*(C'\fR,
+\&\*(fC\*(C`xgene1\*(C'\fR
+\&\*(fC\*(C`xgene2\*(C'\fR,
+\&\*(fC\*(C`cortex\-r82\*(C'\fR,
+\&\*(fC\*(C`cortex\-x1\*(C'\fR,
+\&\*(fC\*(C`cortex\-x2\*(C'\fR,
+\&\*(fC\*(C`cortex\-x3\*(C'\fR,
and
-\&\f(CW\*(C`cortex\-x4\*(C'\fR.
-The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to
accept
+\&\*(fC\*(C`cortex\-x4\*(C'\fR.
+The special name \*(fC\*(C`all\*(C'\fR may be used to allow the assembler to
accept
instructions valid for any supported processor, including all optional
extensions.
.Sp
@@ -883,7 +904,7 @@ accept, or restrict, various extension m
processor.
.Sp
If some implementations of a particular processor can have an
-extension, then then those extensions are automatically enabled.
+extension, then those extensions are automatically enabled.
Consequently, you will not normally have to specify any additional
extensions.
.IP \fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
@@ -891,11 +912,11 @@ extensions.
This option specifies the target architecture. The assembler will
issue an error message if an attempt is made to assemble an
instruction which will not execute on the target architecture. The
-following architecture names are recognized: \f(CW\*(C`armv8\-a\*(C'\fR,
-\&\f(CW\*(C`armv8.1\-a\*(C'\fR, \f(CW\*(C`armv8.2\-a\*(C'\fR,
\f(CW\*(C`armv8.3\-a\*(C'\fR, \f(CW\*(C`armv8.4\-a\*(C'\fR
-\&\f(CW\*(C`armv8.5\-a\*(C'\fR, \f(CW\*(C`armv8.6\-a\*(C'\fR,
\f(CW\*(C`armv8.7\-a\*(C'\fR, \f(CW\*(C`armv8.8\-a\*(C'\fR,
-\&\f(CW\*(C`armv8.9\-a\*(C'\fR, \f(CW\*(C`armv8\-r\*(C'\fR,
\f(CW\*(C`armv9\-a\*(C'\fR, \f(CW\*(C`armv9.1\-a\*(C'\fR,
-\&\f(CW\*(C`armv9.2\-a\*(C'\fR, \f(CW\*(C`armv9.3\-a\*(C'\fR,
\f(CW\*(C`armv9.4\-a\*(C'\fR and \f(CW\*(C`armv9.5\-a\*(C'\fR.
+following architecture names are recognized: \*(fC\*(C`armv8\-a\*(C'\fR,
+\&\*(fC\*(C`armv8.1\-a\*(C'\fR, \*(fC\*(C`armv8.2\-a\*(C'\fR,
\*(fC\*(C`armv8.3\-a\*(C'\fR, \*(fC\*(C`armv8.4\-a\*(C'\fR
+\&\*(fC\*(C`armv8.5\-a\*(C'\fR, \*(fC\*(C`armv8.6\-a\*(C'\fR,
\*(fC\*(C`armv8.7\-a\*(C'\fR, \*(fC\*(C`armv8.8\-a\*(C'\fR,
+\&\*(fC\*(C`armv8.9\-a\*(C'\fR, \*(fC\*(C`armv8\-r\*(C'\fR,
\*(fC\*(C`armv9\-a\*(C'\fR, \*(fC\*(C`armv9.1\-a\*(C'\fR,
+\&\*(fC\*(C`armv9.2\-a\*(C'\fR, \*(fC\*(C`armv9.3\-a\*(C'\fR,
\*(fC\*(C`armv9.4\-a\*(C'\fR and \*(fC\*(C`armv9.5\-a\*(C'\fR.
.Sp
If both \fB\-mcpu\fR and \fB\-march\fR are specified, the
assembler will use the setting for \fB\-mcpu\fR. If neither are
@@ -919,44 +940,44 @@ processor.
This option specifies the target processor. If an attempt is made to
assemble an instruction which will not execute on the target processor,
the assembler may either expand the instruction as a macro or issue an
-error message. This option is equivalent to the \f(CW\*(C`.arch\*(C'\fR
directive.
+error message. This option is equivalent to the \*(fC\*(C`.arch\*(C'\fR
directive.
.Sp
The following processor names are recognized:
-\&\f(CW21064\fR,
-\&\f(CW\*(C`21064a\*(C'\fR,
-\&\f(CW21066\fR,
-\&\f(CW21068\fR,
-\&\f(CW21164\fR,
-\&\f(CW\*(C`21164a\*(C'\fR,
-\&\f(CW\*(C`21164pc\*(C'\fR,
-\&\f(CW21264\fR,
-\&\f(CW\*(C`21264a\*(C'\fR,
-\&\f(CW\*(C`21264b\*(C'\fR,
-\&\f(CW\*(C`ev4\*(C'\fR,
-\&\f(CW\*(C`ev5\*(C'\fR,
-\&\f(CW\*(C`lca45\*(C'\fR,
-\&\f(CW\*(C`ev5\*(C'\fR,
-\&\f(CW\*(C`ev56\*(C'\fR,
-\&\f(CW\*(C`pca56\*(C'\fR,
-\&\f(CW\*(C`ev6\*(C'\fR,
-\&\f(CW\*(C`ev67\*(C'\fR,
-\&\f(CW\*(C`ev68\*(C'\fR.
-The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to
accept
+\&\*(fC21064\fR,
+\&\*(fC\*(C`21064a\*(C'\fR,
+\&\*(fC21066\fR,
+\&\*(fC21068\fR,
+\&\*(fC21164\fR,
+\&\*(fC\*(C`21164a\*(C'\fR,
+\&\*(fC\*(C`21164pc\*(C'\fR,
+\&\*(fC21264\fR,
+\&\*(fC\*(C`21264a\*(C'\fR,
+\&\*(fC\*(C`21264b\*(C'\fR,
+\&\*(fC\*(C`ev4\*(C'\fR,
+\&\*(fC\*(C`ev5\*(C'\fR,
+\&\*(fC\*(C`lca45\*(C'\fR,
+\&\*(fC\*(C`ev5\*(C'\fR,
+\&\*(fC\*(C`ev56\*(C'\fR,
+\&\*(fC\*(C`pca56\*(C'\fR,
+\&\*(fC\*(C`ev6\*(C'\fR,
+\&\*(fC\*(C`ev67\*(C'\fR,
+\&\*(fC\*(C`ev68\*(C'\fR.
+The special name \*(fC\*(C`all\*(C'\fR may be used to allow the assembler to
accept
instructions valid for any Alpha processor.
.Sp
-In order to support existing practice in OSF/1 with respect to
\f(CW\*(C`.arch\*(C'\fR,
+In order to support existing practice in OSF/1 with respect to
\*(fC\*(C`.arch\*(C'\fR,
and existing practice within \fBMILO\fR (the Linux ARC bootloader), the
-numbered processor names (e.g. 21064) enable the processor-specific PALcode
-instructions, while the "electro-vlasic" names (e.g. \f(CW\*(C`ev4\*(C'\fR) do
not.
+numbered processor names (e.g.\& 21064) enable the processor-specific PALcode
+instructions, while the "electro-vlasic" names (e.g.\& \*(fC\*(C`ev4\*(C'\fR)
do not.
.IP \fB\-mdebug\fR 4
.IX Item "-mdebug"
.PD 0
.IP \fB\-no\-mdebug\fR 4
.IX Item "-no-mdebug"
.PD
-Enables or disables the generation of \f(CW\*(C`.mdebug\*(C'\fR encapsulation
for
+Enables or disables the generation of \*(fC\*(C`.mdebug\*(C'\fR encapsulation
for
stabs directives and procedure descriptors. The default is to automatically
-enable \f(CW\*(C`.mdebug\*(C'\fR when the first stabs directive is seen.
+enable \*(fC\*(C`.mdebug\*(C'\fR when the first stabs directive is seen.
.IP \fB\-relax\fR 4
.IX Item "-relax"
This option forces all relocations to be put into the object file, instead
@@ -972,7 +993,7 @@ can still be useful in specific applicat
.PD
Enables or disables the optimization of procedure calls, both at assemblage
and at link time. These options are only available for VMS targets and
-\&\f(CW\*(C`\-replace\*(C'\fR is the default. See section 1.4.1 of the
OpenVMS Linker
+\&\*(fC\*(C`\-replace\*(C'\fR is the default. See section 1.4.1 of the
OpenVMS Linker
Utility Manual.
.IP \fB\-g\fR 4
.IX Item "-g"
@@ -982,8 +1003,8 @@ information for ECOFF, local labels must
file. Otherwise this option has no effect.
.IP \fB\-G\fR\fIsize\fR 4
.IX Item "-Gsize"
-A local common symbol larger than \fIsize\fR is placed in
\f(CW\*(C`.bss\*(C'\fR,
-while smaller symbols are placed in \f(CW\*(C`.sbss\*(C'\fR.
+A local common symbol larger than \fIsize\fR is placed in
\*(fC\*(C`.bss\*(C'\fR,
+while smaller symbols are placed in \*(fC\*(C`.sbss\*(C'\fR.
.IP \fB\-F\fR 4
.IX Item "-F"
.PD 0
@@ -1044,44 +1065,44 @@ the Blackfin processor family.
.IX Item "-mcpu=processor[-sirevision]"
This option specifies the target processor. The optional \fIsirevision\fR
is not used in assembler. It's here such that GCC can easily pass down its
-\&\f(CW\*(C`\-mcpu=\*(C'\fR option. The assembler will issue an
+\&\*(fC\*(C`\-mcpu=\*(C'\fR option. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
recognized:
-\&\f(CW\*(C`bf504\*(C'\fR,
-\&\f(CW\*(C`bf506\*(C'\fR,
-\&\f(CW\*(C`bf512\*(C'\fR,
-\&\f(CW\*(C`bf514\*(C'\fR,
-\&\f(CW\*(C`bf516\*(C'\fR,
-\&\f(CW\*(C`bf518\*(C'\fR,
-\&\f(CW\*(C`bf522\*(C'\fR,
-\&\f(CW\*(C`bf523\*(C'\fR,
-\&\f(CW\*(C`bf524\*(C'\fR,
-\&\f(CW\*(C`bf525\*(C'\fR,
-\&\f(CW\*(C`bf526\*(C'\fR,
-\&\f(CW\*(C`bf527\*(C'\fR,
-\&\f(CW\*(C`bf531\*(C'\fR,
-\&\f(CW\*(C`bf532\*(C'\fR,
-\&\f(CW\*(C`bf533\*(C'\fR,
-\&\f(CW\*(C`bf534\*(C'\fR,
-\&\f(CW\*(C`bf535\*(C'\fR (not implemented yet),
-\&\f(CW\*(C`bf536\*(C'\fR,
-\&\f(CW\*(C`bf537\*(C'\fR,
-\&\f(CW\*(C`bf538\*(C'\fR,
-\&\f(CW\*(C`bf539\*(C'\fR,
-\&\f(CW\*(C`bf542\*(C'\fR,
-\&\f(CW\*(C`bf542m\*(C'\fR,
-\&\f(CW\*(C`bf544\*(C'\fR,
-\&\f(CW\*(C`bf544m\*(C'\fR,
-\&\f(CW\*(C`bf547\*(C'\fR,
-\&\f(CW\*(C`bf547m\*(C'\fR,
-\&\f(CW\*(C`bf548\*(C'\fR,
-\&\f(CW\*(C`bf548m\*(C'\fR,
-\&\f(CW\*(C`bf549\*(C'\fR,
-\&\f(CW\*(C`bf549m\*(C'\fR,
-\&\f(CW\*(C`bf561\*(C'\fR,
+\&\*(fC\*(C`bf504\*(C'\fR,
+\&\*(fC\*(C`bf506\*(C'\fR,
+\&\*(fC\*(C`bf512\*(C'\fR,
+\&\*(fC\*(C`bf514\*(C'\fR,
+\&\*(fC\*(C`bf516\*(C'\fR,
+\&\*(fC\*(C`bf518\*(C'\fR,
+\&\*(fC\*(C`bf522\*(C'\fR,
+\&\*(fC\*(C`bf523\*(C'\fR,
+\&\*(fC\*(C`bf524\*(C'\fR,
+\&\*(fC\*(C`bf525\*(C'\fR,
+\&\*(fC\*(C`bf526\*(C'\fR,
+\&\*(fC\*(C`bf527\*(C'\fR,
+\&\*(fC\*(C`bf531\*(C'\fR,
+\&\*(fC\*(C`bf532\*(C'\fR,
+\&\*(fC\*(C`bf533\*(C'\fR,
+\&\*(fC\*(C`bf534\*(C'\fR,
+\&\*(fC\*(C`bf535\*(C'\fR (not implemented yet),
+\&\*(fC\*(C`bf536\*(C'\fR,
+\&\*(fC\*(C`bf537\*(C'\fR,
+\&\*(fC\*(C`bf538\*(C'\fR,
+\&\*(fC\*(C`bf539\*(C'\fR,
+\&\*(fC\*(C`bf542\*(C'\fR,
+\&\*(fC\*(C`bf542m\*(C'\fR,
+\&\*(fC\*(C`bf544\*(C'\fR,
+\&\*(fC\*(C`bf544m\*(C'\fR,
+\&\*(fC\*(C`bf547\*(C'\fR,
+\&\*(fC\*(C`bf547m\*(C'\fR,
+\&\*(fC\*(C`bf548\*(C'\fR,
+\&\*(fC\*(C`bf548m\*(C'\fR,
+\&\*(fC\*(C`bf549\*(C'\fR,
+\&\*(fC\*(C`bf549m\*(C'\fR,
+\&\*(fC\*(C`bf561\*(C'\fR,
and
-\&\f(CW\*(C`bf592\*(C'\fR.
+\&\*(fC\*(C`bf592\*(C'\fR.
.IP \fB\-mfdpic\fR 4
.IX Item "-mfdpic"
Assemble for the FDPIC ABI.
@@ -1096,8 +1117,8 @@ Disable \-mfdpic.
The following options are available when as is configured for
the Linux kernel BPF processor family.
.PP
-\&\f(CW@chapter\fR BPF Dependent Features
-.SS "BPF Options"
+\&\*(fC@chapter\fR BPF Dependent Features
+.SS BPF Options
.IX Subsection "BPF Options"
.IP \fB\-EB\fR 4
.IX Item "-EB"
@@ -1165,9 +1186,9 @@ Generate position-independent code.
.IX Item "-mno-ljump"
.PD
Enable/disable transformation of the short branch instructions
-\&\f(CW\*(C`jbf\*(C'\fR, \f(CW\*(C`jbt\*(C'\fR, and \f(CW\*(C`jbr\*(C'\fR to
\f(CW\*(C`jmpi\*(C'\fR.
+\&\*(fC\*(C`jbf\*(C'\fR, \*(fC\*(C`jbt\*(C'\fR, and \*(fC\*(C`jbr\*(C'\fR to
\*(fC\*(C`jmpi\*(C'\fR.
This option is for V2 processors only.
-It is ignored on CK801 and CK802 targets, which do not support the
\f(CW\*(C`jmpi\*(C'\fR
+It is ignored on CK801 and CK802 targets, which do not support the
\*(fC\*(C`jmpi\*(C'\fR
instruction, and is enabled by default for other processors.
.IP \fB\-mbranch\-stub\fR 4
.IX Item "-mbranch-stub"
@@ -1175,7 +1196,7 @@ instruction, and is enabled by default f
.IP \fB\-mno\-branch\-stub\fR 4
.IX Item "-mno-branch-stub"
.PD
-Pass through \f(CW\*(C`R_CKCORE_PCREL_IMM26BY2\*(C'\fR relocations for
\f(CW\*(C`bsr\*(C'\fR
+Pass through \*(fC\*(C`R_CKCORE_PCREL_IMM26BY2\*(C'\fR relocations for
\*(fC\*(C`bsr\*(C'\fR
instructions to the linker.
.Sp
This option is only available for bare-metal C\-SKY V2 ELF targets,
@@ -1191,7 +1212,7 @@ dynamically linked against shared librar
.IP \fB\-mno\-force2bsr\fR 4
.IX Item "-mno-force2bsr"
.PD
-Enable/disable transformation of \f(CW\*(C`jbsr\*(C'\fR instructions to
\f(CW\*(C`bsr\*(C'\fR.
+Enable/disable transformation of \*(fC\*(C`jbsr\*(C'\fR instructions to
\*(fC\*(C`bsr\*(C'\fR.
This option is always enabled (and \fB\-mno\-force2bsr\fR is ignored)
for CK801/CK802 targets. It is also always enabled when
\&\fB\-mbranch\-stub\fR is in effect.
@@ -1205,7 +1226,7 @@ for CK801/CK802 targets. It is also alw
.IP \fB\-mno\-jsri2bsr\fR 4
.IX Item "-mno-jsri2bsr"
.PD
-Enable/disable transformation of \f(CW\*(C`jsri\*(C'\fR instructions to
\f(CW\*(C`bsr\*(C'\fR.
+Enable/disable transformation of \*(fC\*(C`jsri\*(C'\fR instructions to
\*(fC\*(C`bsr\*(C'\fR.
This option is enabled by default.
.IP \fB\-mnolrw\fR 4
.IX Item "-mnolrw"
@@ -1213,15 +1234,15 @@ This option is enabled by default.
.IP \fB\-mno\-lrw\fR 4
.IX Item "-mno-lrw"
.PD
-Enable/disable transformation of \f(CW\*(C`lrw\*(C'\fR instructions into a
-\&\f(CW\*(C`movih\*(C'\fR/\f(CW\*(C`ori\*(C'\fR pair.
+Enable/disable transformation of \*(fC\*(C`lrw\*(C'\fR instructions into a
+\&\*(fC\*(C`movih\*(C'\fR/\*(fC\*(C`ori\*(C'\fR pair.
.IP \fB\-melrw\fR 4
.IX Item "-melrw"
.PD 0
.IP \fB\-mno\-elrw\fR 4
.IX Item "-mno-elrw"
.PD
-Enable/disable extended \f(CW\*(C`lrw\*(C'\fR instructions.
+Enable/disable extended \*(fC\*(C`lrw\*(C'\fR instructions.
This option is enabled by default for CK800\-series processors.
.IP \fB\-mlaf\fR 4
.IX Item "-mlaf"
@@ -1256,7 +1277,7 @@ Enable/disable interrupt stack instructi
default on CK801, CK802, and CK802 processors.
.PP
The following options explicitly enable certain optional instructions.
-These features are also enabled implicitly by using \f(CW\*(C`\-mcpu=\*(C'\fR
to specify
+These features are also enabled implicitly by using \*(fC\*(C`\-mcpu=\*(C'\fR
to specify
a processor that supports it.
.IP \fB\-mhard\-float\fR 4
.IX Item "-mhard-float"
@@ -1290,18 +1311,18 @@ The following options are available when
an Epiphany processor.
.IP \fB\-mepiphany\fR 4
.IX Item "-mepiphany"
-Specifies that the both 32 and 16 bit instructions are allowed. This is the
+Specifies that the both 32- and 16-bit instructions are allowed. This is the
default behavior.
.IP \fB\-mepiphany16\fR 4
.IX Item "-mepiphany16"
-Restricts the permitted instructions to just the 16 bit set.
+Restricts the permitted instructions to just the 16-bit set.
.PP
The following options are available when as is configured for an H8/300
processor.
-\&\f(CW@chapter\fR H8/300 Dependent Features
+\&\*(fC@chapter\fR H8/300 Dependent Features
.SS Options
.IX Subsection "Options"
-The Renesas H8/300 version of \f(CW\*(C`as\*(C'\fR has one
+The Renesas H8/300 version of \*(fC\*(C`as\*(C'\fR has one
machine-dependent option:
.IP \fB\-h\-tick\-hex\fR 4
.IX Item "-h-tick-hex"
@@ -1310,12 +1331,12 @@ Support H'00 style hex constants in addi
.IX Item "-mach=name"
Sets the H8300 machine variant. The following machine names
are recognised:
-\&\f(CW\*(C`h8300h\*(C'\fR,
-\&\f(CW\*(C`h8300hn\*(C'\fR,
-\&\f(CW\*(C`h8300s\*(C'\fR,
-\&\f(CW\*(C`h8300sn\*(C'\fR,
-\&\f(CW\*(C`h8300sx\*(C'\fR and
-\&\f(CW\*(C`h8300sxn\*(C'\fR.
+\&\*(fC\*(C`h8300h\*(C'\fR,
+\&\*(fC\*(C`h8300hn\*(C'\fR,
+\&\*(fC\*(C`h8300s\*(C'\fR,
+\&\*(fC\*(C`h8300sn\*(C'\fR,
+\&\*(fC\*(C`h8300sx\*(C'\fR and
+\&\*(fC\*(C`h8300sxn\*(C'\fR.
.PP
The following options are available when as is configured for
an i386 processor.
@@ -1349,209 +1370,209 @@ This option specifies the target process
issue an error message if an attempt is made to assemble an instruction
which will not execute on the target processor. The following
processor names are recognized:
-\&\f(CW\*(C`i8086\*(C'\fR,
-\&\f(CW\*(C`i186\*(C'\fR,
-\&\f(CW\*(C`i286\*(C'\fR,
-\&\f(CW\*(C`i386\*(C'\fR,
-\&\f(CW\*(C`i486\*(C'\fR,
-\&\f(CW\*(C`i586\*(C'\fR,
-\&\f(CW\*(C`i686\*(C'\fR,
-\&\f(CW\*(C`pentium\*(C'\fR,
-\&\f(CW\*(C`pentiumpro\*(C'\fR,
-\&\f(CW\*(C`pentiumii\*(C'\fR,
-\&\f(CW\*(C`pentiumiii\*(C'\fR,
-\&\f(CW\*(C`pentium4\*(C'\fR,
-\&\f(CW\*(C`prescott\*(C'\fR,
-\&\f(CW\*(C`nocona\*(C'\fR,
-\&\f(CW\*(C`core\*(C'\fR,
-\&\f(CW\*(C`core2\*(C'\fR,
-\&\f(CW\*(C`corei7\*(C'\fR,
-\&\f(CW\*(C`iamcu\*(C'\fR,
-\&\f(CW\*(C`k6\*(C'\fR,
-\&\f(CW\*(C`k6_2\*(C'\fR,
-\&\f(CW\*(C`athlon\*(C'\fR,
-\&\f(CW\*(C`opteron\*(C'\fR,
-\&\f(CW\*(C`k8\*(C'\fR,
-\&\f(CW\*(C`amdfam10\*(C'\fR,
-\&\f(CW\*(C`bdver1\*(C'\fR,
-\&\f(CW\*(C`bdver2\*(C'\fR,
-\&\f(CW\*(C`bdver3\*(C'\fR,
-\&\f(CW\*(C`bdver4\*(C'\fR,
-\&\f(CW\*(C`znver1\*(C'\fR,
-\&\f(CW\*(C`znver2\*(C'\fR,
-\&\f(CW\*(C`znver3\*(C'\fR,
-\&\f(CW\*(C`znver4\*(C'\fR,
-\&\f(CW\*(C`znver5\*(C'\fR,
-\&\f(CW\*(C`btver1\*(C'\fR,
-\&\f(CW\*(C`btver2\*(C'\fR,
-\&\f(CW\*(C`generic32\*(C'\fR and
-\&\f(CW\*(C`generic64\*(C'\fR.
+\&\*(fC\*(C`i8086\*(C'\fR,
+\&\*(fC\*(C`i186\*(C'\fR,
+\&\*(fC\*(C`i286\*(C'\fR,
+\&\*(fC\*(C`i386\*(C'\fR,
+\&\*(fC\*(C`i486\*(C'\fR,
+\&\*(fC\*(C`i586\*(C'\fR,
+\&\*(fC\*(C`i686\*(C'\fR,
+\&\*(fC\*(C`pentium\*(C'\fR,
+\&\*(fC\*(C`pentiumpro\*(C'\fR,
+\&\*(fC\*(C`pentiumii\*(C'\fR,
+\&\*(fC\*(C`pentiumiii\*(C'\fR,
+\&\*(fC\*(C`pentium4\*(C'\fR,
+\&\*(fC\*(C`prescott\*(C'\fR,
+\&\*(fC\*(C`nocona\*(C'\fR,
+\&\*(fC\*(C`core\*(C'\fR,
+\&\*(fC\*(C`core2\*(C'\fR,
+\&\*(fC\*(C`corei7\*(C'\fR,
+\&\*(fC\*(C`iamcu\*(C'\fR,
+\&\*(fC\*(C`k6\*(C'\fR,
+\&\*(fC\*(C`k6_2\*(C'\fR,
+\&\*(fC\*(C`athlon\*(C'\fR,
+\&\*(fC\*(C`opteron\*(C'\fR,
+\&\*(fC\*(C`k8\*(C'\fR,
+\&\*(fC\*(C`amdfam10\*(C'\fR,
+\&\*(fC\*(C`bdver1\*(C'\fR,
+\&\*(fC\*(C`bdver2\*(C'\fR,
+\&\*(fC\*(C`bdver3\*(C'\fR,
+\&\*(fC\*(C`bdver4\*(C'\fR,
+\&\*(fC\*(C`znver1\*(C'\fR,
+\&\*(fC\*(C`znver2\*(C'\fR,
+\&\*(fC\*(C`znver3\*(C'\fR,
+\&\*(fC\*(C`znver4\*(C'\fR,
+\&\*(fC\*(C`znver5\*(C'\fR,
+\&\*(fC\*(C`btver1\*(C'\fR,
+\&\*(fC\*(C`btver2\*(C'\fR,
+\&\*(fC\*(C`generic32\*(C'\fR and
+\&\*(fC\*(C`generic64\*(C'\fR.
.Sp
In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics. For example,
-\&\f(CW\*(C`\-march=i686+sse4+vmx\*(C'\fR extends \fIi686\fR with \fIsse4\fR
and
+\&\*(fC\*(C`\-march=i686+sse4+vmx\*(C'\fR extends \fIi686\fR with \fIsse4\fR
and
\&\fIvmx\fR. The following extensions are currently supported:
-\&\f(CW8087\fR,
-\&\f(CW287\fR,
-\&\f(CW387\fR,
-\&\f(CW687\fR,
-\&\f(CW\*(C`cmov\*(C'\fR,
-\&\f(CW\*(C`fxsr\*(C'\fR,
-\&\f(CW\*(C`mmx\*(C'\fR,
-\&\f(CW\*(C`sse\*(C'\fR,
-\&\f(CW\*(C`sse2\*(C'\fR,
-\&\f(CW\*(C`sse3\*(C'\fR,
-\&\f(CW\*(C`sse4a\*(C'\fR,
-\&\f(CW\*(C`ssse3\*(C'\fR,
-\&\f(CW\*(C`sse4.1\*(C'\fR,
-\&\f(CW\*(C`sse4.2\*(C'\fR,
-\&\f(CW\*(C`sse4\*(C'\fR,
-\&\f(CW\*(C`avx\*(C'\fR,
-\&\f(CW\*(C`avx2\*(C'\fR,
-\&\f(CW\*(C`lahf_sahf\*(C'\fR,
-\&\f(CW\*(C`monitor\*(C'\fR,
-\&\f(CW\*(C`adx\*(C'\fR,
-\&\f(CW\*(C`rdseed\*(C'\fR,
-\&\f(CW\*(C`prfchw\*(C'\fR,
-\&\f(CW\*(C`smap\*(C'\fR,
-\&\f(CW\*(C`mpx\*(C'\fR,
-\&\f(CW\*(C`sha\*(C'\fR,
-\&\f(CW\*(C`rdpid\*(C'\fR,
-\&\f(CW\*(C`ptwrite\*(C'\fR,
-\&\f(CW\*(C`cet\*(C'\fR,
-\&\f(CW\*(C`gfni\*(C'\fR,
-\&\f(CW\*(C`vaes\*(C'\fR,
-\&\f(CW\*(C`vpclmulqdq\*(C'\fR,
-\&\f(CW\*(C`prefetchwt1\*(C'\fR,
-\&\f(CW\*(C`clflushopt\*(C'\fR,
-\&\f(CW\*(C`se1\*(C'\fR,
-\&\f(CW\*(C`clwb\*(C'\fR,
-\&\f(CW\*(C`movdiri\*(C'\fR,
-\&\f(CW\*(C`movdir64b\*(C'\fR,
-\&\f(CW\*(C`enqcmd\*(C'\fR,
-\&\f(CW\*(C`serialize\*(C'\fR,
-\&\f(CW\*(C`tsxldtrk\*(C'\fR,
-\&\f(CW\*(C`kl\*(C'\fR,
-\&\f(CW\*(C`widekl\*(C'\fR,
-\&\f(CW\*(C`hreset\*(C'\fR,
-\&\f(CW\*(C`avx512f\*(C'\fR,
-\&\f(CW\*(C`avx512cd\*(C'\fR,
-\&\f(CW\*(C`avx512er\*(C'\fR,
-\&\f(CW\*(C`avx512pf\*(C'\fR,
-\&\f(CW\*(C`avx512vl\*(C'\fR,
-\&\f(CW\*(C`avx512bw\*(C'\fR,
-\&\f(CW\*(C`avx512dq\*(C'\fR,
-\&\f(CW\*(C`avx512ifma\*(C'\fR,
-\&\f(CW\*(C`avx512vbmi\*(C'\fR,
-\&\f(CW\*(C`avx512_4fmaps\*(C'\fR,
-\&\f(CW\*(C`avx512_4vnniw\*(C'\fR,
-\&\f(CW\*(C`avx512_vpopcntdq\*(C'\fR,
-\&\f(CW\*(C`avx512_vbmi2\*(C'\fR,
-\&\f(CW\*(C`avx512_vnni\*(C'\fR,
-\&\f(CW\*(C`avx512_bitalg\*(C'\fR,
-\&\f(CW\*(C`avx512_vp2intersect\*(C'\fR,
-\&\f(CW\*(C`tdx\*(C'\fR,
-\&\f(CW\*(C`avx512_bf16\*(C'\fR,
-\&\f(CW\*(C`avx_vnni\*(C'\fR,
-\&\f(CW\*(C`avx512_fp16\*(C'\fR,
-\&\f(CW\*(C`prefetchi\*(C'\fR,
-\&\f(CW\*(C`avx_ifma\*(C'\fR,
-\&\f(CW\*(C`avx_vnni_int8\*(C'\fR,
-\&\f(CW\*(C`cmpccxadd\*(C'\fR,
-\&\f(CW\*(C`wrmsrns\*(C'\fR,
-\&\f(CW\*(C`msrlist\*(C'\fR,
-\&\f(CW\*(C`avx_ne_convert\*(C'\fR,
-\&\f(CW\*(C`rao_int\*(C'\fR,
-\&\f(CW\*(C`fred\*(C'\fR,
-\&\f(CW\*(C`lkgs\*(C'\fR,
-\&\f(CW\*(C`avx_vnni_int16\*(C'\fR,
-\&\f(CW\*(C`sha512\*(C'\fR,
-\&\f(CW\*(C`sm3\*(C'\fR,
-\&\f(CW\*(C`sm4\*(C'\fR,
-\&\f(CW\*(C`pbndkb\*(C'\fR,
-\&\f(CW\*(C`avx10.1\*(C'\fR,
-\&\f(CW\*(C`avx10.1/512\*(C'\fR,
-\&\f(CW\*(C`avx10.1/256\*(C'\fR,
-\&\f(CW\*(C`avx10.1/128\*(C'\fR,
-\&\f(CW\*(C`user_msr\*(C'\fR,
-\&\f(CW\*(C`msr_imm\*(C'\fR,
-\&\f(CW\*(C`apx_f\*(C'\fR,
-\&\f(CW\*(C`avx10.2\*(C'\fR,
-\&\f(CW\*(C`avx10.2/512\*(C'\fR,
-\&\f(CW\*(C`avx10.2/256\*(C'\fR,
-\&\f(CW\*(C`avx10.2/128\*(C'\fR,
-\&\f(CW\*(C`movrs\*(C'\fR,
-\&\f(CW\*(C`amx_int8\*(C'\fR,
-\&\f(CW\*(C`amx_bf16\*(C'\fR,
-\&\f(CW\*(C`amx_fp16\*(C'\fR,
-\&\f(CW\*(C`amx_complex\*(C'\fR,
-\&\f(CW\*(C`amx_transpose\*(C'\fR,
-\&\f(CW\*(C`amx_tf32\*(C'\fR,
-\&\f(CW\*(C`amx_fp8\*(C'\fR
-\&\f(CW\*(C`amx_movrs\*(C'\fR,
-\&\f(CW\*(C`amx_avx512\*(C'\fR,
-\&\f(CW\*(C`amx_tile\*(C'\fR,
-\&\f(CW\*(C`vmx\*(C'\fR,
-\&\f(CW\*(C`vmfunc\*(C'\fR,
-\&\f(CW\*(C`smx\*(C'\fR,
-\&\f(CW\*(C`xsave\*(C'\fR,
-\&\f(CW\*(C`xsaveopt\*(C'\fR,
-\&\f(CW\*(C`xsavec\*(C'\fR,
-\&\f(CW\*(C`xsaves\*(C'\fR,
-\&\f(CW\*(C`aes\*(C'\fR,
-\&\f(CW\*(C`pclmul\*(C'\fR,
-\&\f(CW\*(C`fsgsbase\*(C'\fR,
-\&\f(CW\*(C`rdrnd\*(C'\fR,
-\&\f(CW\*(C`f16c\*(C'\fR,
-\&\f(CW\*(C`bmi2\*(C'\fR,
-\&\f(CW\*(C`fma\*(C'\fR,
-\&\f(CW\*(C`movbe\*(C'\fR,
-\&\f(CW\*(C`ept\*(C'\fR,
-\&\f(CW\*(C`lzcnt\*(C'\fR,
-\&\f(CW\*(C`popcnt\*(C'\fR,
-\&\f(CW\*(C`hle\*(C'\fR,
-\&\f(CW\*(C`rtm\*(C'\fR,
-\&\f(CW\*(C`tsx\*(C'\fR,
-\&\f(CW\*(C`invpcid\*(C'\fR,
-\&\f(CW\*(C`clflush\*(C'\fR,
-\&\f(CW\*(C`mwaitx\*(C'\fR,
-\&\f(CW\*(C`clzero\*(C'\fR,
-\&\f(CW\*(C`wbnoinvd\*(C'\fR,
-\&\f(CW\*(C`pconfig\*(C'\fR,
-\&\f(CW\*(C`waitpkg\*(C'\fR,
-\&\f(CW\*(C`uintr\*(C'\fR,
-\&\f(CW\*(C`cldemote\*(C'\fR,
-\&\f(CW\*(C`rdpru\*(C'\fR,
-\&\f(CW\*(C`mcommit\*(C'\fR,
-\&\f(CW\*(C`sev_es\*(C'\fR,
-\&\f(CW\*(C`lwp\*(C'\fR,
-\&\f(CW\*(C`fma4\*(C'\fR,
-\&\f(CW\*(C`xop\*(C'\fR,
-\&\f(CW\*(C`cx16\*(C'\fR,
-\&\f(CW\*(C`syscall\*(C'\fR,
-\&\f(CW\*(C`rdtscp\*(C'\fR,
-\&\f(CW\*(C`3dnow\*(C'\fR,
-\&\f(CW\*(C`3dnowa\*(C'\fR,
-\&\f(CW\*(C`sse4a\*(C'\fR,
-\&\f(CW\*(C`sse5\*(C'\fR,
-\&\f(CW\*(C`snp\*(C'\fR,
-\&\f(CW\*(C`invlpgb\*(C'\fR,
-\&\f(CW\*(C`tlbsync\*(C'\fR,
-\&\f(CW\*(C`svme\*(C'\fR,
-\&\f(CW\*(C`gmism2\*(C'\fR,
-\&\f(CW\*(C`gmiccs\*(C'\fR,
-\&\f(CW\*(C`padlockrng2\*(C'\fR,
-\&\f(CW\*(C`padlockphe2\*(C'\fR and
-\&\f(CW\*(C`padlock\*(C'\fR.
-Note that these extension mnemonics can be prefixed with \f(CW\*(C`no\*(C'\fR
to revoke
+\&\*(fC8087\fR,
+\&\*(fC287\fR,
+\&\*(fC387\fR,
+\&\*(fC687\fR,
+\&\*(fC\*(C`cmov\*(C'\fR,
+\&\*(fC\*(C`fxsr\*(C'\fR,
+\&\*(fC\*(C`mmx\*(C'\fR,
+\&\*(fC\*(C`sse\*(C'\fR,
+\&\*(fC\*(C`sse2\*(C'\fR,
+\&\*(fC\*(C`sse3\*(C'\fR,
+\&\*(fC\*(C`sse4a\*(C'\fR,
+\&\*(fC\*(C`ssse3\*(C'\fR,
+\&\*(fC\*(C`sse4.1\*(C'\fR,
+\&\*(fC\*(C`sse4.2\*(C'\fR,
+\&\*(fC\*(C`sse4\*(C'\fR,
+\&\*(fC\*(C`avx\*(C'\fR,
+\&\*(fC\*(C`avx2\*(C'\fR,
+\&\*(fC\*(C`lahf_sahf\*(C'\fR,
+\&\*(fC\*(C`monitor\*(C'\fR,
+\&\*(fC\*(C`adx\*(C'\fR,
+\&\*(fC\*(C`rdseed\*(C'\fR,
+\&\*(fC\*(C`prfchw\*(C'\fR,
+\&\*(fC\*(C`smap\*(C'\fR,
+\&\*(fC\*(C`mpx\*(C'\fR,
+\&\*(fC\*(C`sha\*(C'\fR,
+\&\*(fC\*(C`rdpid\*(C'\fR,
+\&\*(fC\*(C`ptwrite\*(C'\fR,
+\&\*(fC\*(C`cet\*(C'\fR,
+\&\*(fC\*(C`gfni\*(C'\fR,
+\&\*(fC\*(C`vaes\*(C'\fR,
+\&\*(fC\*(C`vpclmulqdq\*(C'\fR,
+\&\*(fC\*(C`prefetchwt1\*(C'\fR,
+\&\*(fC\*(C`clflushopt\*(C'\fR,
+\&\*(fC\*(C`se1\*(C'\fR,
+\&\*(fC\*(C`clwb\*(C'\fR,
+\&\*(fC\*(C`movdiri\*(C'\fR,
+\&\*(fC\*(C`movdir64b\*(C'\fR,
+\&\*(fC\*(C`enqcmd\*(C'\fR,
+\&\*(fC\*(C`serialize\*(C'\fR,
+\&\*(fC\*(C`tsxldtrk\*(C'\fR,
+\&\*(fC\*(C`kl\*(C'\fR,
+\&\*(fC\*(C`widekl\*(C'\fR,
+\&\*(fC\*(C`hreset\*(C'\fR,
+\&\*(fC\*(C`avx512f\*(C'\fR,
+\&\*(fC\*(C`avx512cd\*(C'\fR,
+\&\*(fC\*(C`avx512er\*(C'\fR,
+\&\*(fC\*(C`avx512pf\*(C'\fR,
+\&\*(fC\*(C`avx512vl\*(C'\fR,
+\&\*(fC\*(C`avx512bw\*(C'\fR,
+\&\*(fC\*(C`avx512dq\*(C'\fR,
+\&\*(fC\*(C`avx512ifma\*(C'\fR,
+\&\*(fC\*(C`avx512vbmi\*(C'\fR,
+\&\*(fC\*(C`avx512_4fmaps\*(C'\fR,
+\&\*(fC\*(C`avx512_4vnniw\*(C'\fR,
+\&\*(fC\*(C`avx512_vpopcntdq\*(C'\fR,
+\&\*(fC\*(C`avx512_vbmi2\*(C'\fR,
+\&\*(fC\*(C`avx512_vnni\*(C'\fR,
+\&\*(fC\*(C`avx512_bitalg\*(C'\fR,
+\&\*(fC\*(C`avx512_vp2intersect\*(C'\fR,
+\&\*(fC\*(C`tdx\*(C'\fR,
+\&\*(fC\*(C`avx512_bf16\*(C'\fR,
+\&\*(fC\*(C`avx_vnni\*(C'\fR,
+\&\*(fC\*(C`avx512_fp16\*(C'\fR,
+\&\*(fC\*(C`prefetchi\*(C'\fR,
+\&\*(fC\*(C`avx_ifma\*(C'\fR,
+\&\*(fC\*(C`avx_vnni_int8\*(C'\fR,
+\&\*(fC\*(C`cmpccxadd\*(C'\fR,
+\&\*(fC\*(C`wrmsrns\*(C'\fR,
+\&\*(fC\*(C`msrlist\*(C'\fR,
+\&\*(fC\*(C`avx_ne_convert\*(C'\fR,
+\&\*(fC\*(C`rao_int\*(C'\fR,
+\&\*(fC\*(C`fred\*(C'\fR,
+\&\*(fC\*(C`lkgs\*(C'\fR,
+\&\*(fC\*(C`avx_vnni_int16\*(C'\fR,
+\&\*(fC\*(C`sha512\*(C'\fR,
+\&\*(fC\*(C`sm3\*(C'\fR,
+\&\*(fC\*(C`sm4\*(C'\fR,
+\&\*(fC\*(C`pbndkb\*(C'\fR,
+\&\*(fC\*(C`avx10.1\*(C'\fR,
+\&\*(fC\*(C`avx10.1/512\*(C'\fR,
+\&\*(fC\*(C`avx10.1/256\*(C'\fR,
+\&\*(fC\*(C`avx10.1/128\*(C'\fR,
+\&\*(fC\*(C`user_msr\*(C'\fR,
+\&\*(fC\*(C`msr_imm\*(C'\fR,
+\&\*(fC\*(C`apx_f\*(C'\fR,
+\&\*(fC\*(C`avx10.2\*(C'\fR,
+\&\*(fC\*(C`avx10.2/512\*(C'\fR,
+\&\*(fC\*(C`avx10.2/256\*(C'\fR,
+\&\*(fC\*(C`avx10.2/128\*(C'\fR,
+\&\*(fC\*(C`movrs\*(C'\fR,
+\&\*(fC\*(C`amx_int8\*(C'\fR,
+\&\*(fC\*(C`amx_bf16\*(C'\fR,
+\&\*(fC\*(C`amx_fp16\*(C'\fR,
+\&\*(fC\*(C`amx_complex\*(C'\fR,
+\&\*(fC\*(C`amx_transpose\*(C'\fR,
+\&\*(fC\*(C`amx_tf32\*(C'\fR,
+\&\*(fC\*(C`amx_fp8\*(C'\fR
+\&\*(fC\*(C`amx_movrs\*(C'\fR,
+\&\*(fC\*(C`amx_avx512\*(C'\fR,
+\&\*(fC\*(C`amx_tile\*(C'\fR,
+\&\*(fC\*(C`vmx\*(C'\fR,
+\&\*(fC\*(C`vmfunc\*(C'\fR,
+\&\*(fC\*(C`smx\*(C'\fR,
+\&\*(fC\*(C`xsave\*(C'\fR,
+\&\*(fC\*(C`xsaveopt\*(C'\fR,
+\&\*(fC\*(C`xsavec\*(C'\fR,
+\&\*(fC\*(C`xsaves\*(C'\fR,
+\&\*(fC\*(C`aes\*(C'\fR,
+\&\*(fC\*(C`pclmul\*(C'\fR,
+\&\*(fC\*(C`fsgsbase\*(C'\fR,
+\&\*(fC\*(C`rdrnd\*(C'\fR,
+\&\*(fC\*(C`f16c\*(C'\fR,
+\&\*(fC\*(C`bmi2\*(C'\fR,
+\&\*(fC\*(C`fma\*(C'\fR,
+\&\*(fC\*(C`movbe\*(C'\fR,
+\&\*(fC\*(C`ept\*(C'\fR,
+\&\*(fC\*(C`lzcnt\*(C'\fR,
+\&\*(fC\*(C`popcnt\*(C'\fR,
+\&\*(fC\*(C`hle\*(C'\fR,
+\&\*(fC\*(C`rtm\*(C'\fR,
+\&\*(fC\*(C`tsx\*(C'\fR,
+\&\*(fC\*(C`invpcid\*(C'\fR,
+\&\*(fC\*(C`clflush\*(C'\fR,
+\&\*(fC\*(C`mwaitx\*(C'\fR,
+\&\*(fC\*(C`clzero\*(C'\fR,
+\&\*(fC\*(C`wbnoinvd\*(C'\fR,
+\&\*(fC\*(C`pconfig\*(C'\fR,
+\&\*(fC\*(C`waitpkg\*(C'\fR,
+\&\*(fC\*(C`uintr\*(C'\fR,
+\&\*(fC\*(C`cldemote\*(C'\fR,
+\&\*(fC\*(C`rdpru\*(C'\fR,
+\&\*(fC\*(C`mcommit\*(C'\fR,
+\&\*(fC\*(C`sev_es\*(C'\fR,
+\&\*(fC\*(C`lwp\*(C'\fR,
+\&\*(fC\*(C`fma4\*(C'\fR,
+\&\*(fC\*(C`xop\*(C'\fR,
+\&\*(fC\*(C`cx16\*(C'\fR,
+\&\*(fC\*(C`syscall\*(C'\fR,
+\&\*(fC\*(C`rdtscp\*(C'\fR,
+\&\*(fC\*(C`3dnow\*(C'\fR,
+\&\*(fC\*(C`3dnowa\*(C'\fR,
+\&\*(fC\*(C`sse4a\*(C'\fR,
+\&\*(fC\*(C`sse5\*(C'\fR,
+\&\*(fC\*(C`snp\*(C'\fR,
+\&\*(fC\*(C`invlpgb\*(C'\fR,
+\&\*(fC\*(C`tlbsync\*(C'\fR,
+\&\*(fC\*(C`svme\*(C'\fR,
+\&\*(fC\*(C`gmism2\*(C'\fR,
+\&\*(fC\*(C`gmiccs\*(C'\fR,
+\&\*(fC\*(C`padlockrng2\*(C'\fR,
+\&\*(fC\*(C`padlockphe2\*(C'\fR and
+\&\*(fC\*(C`padlock\*(C'\fR.
+Note that these extension mnemonics can be prefixed with \*(fC\*(C`no\*(C'\fR
to revoke
the respective (and any dependent) functionality. Note further that the
-suffixes permitted on \f(CW\*(C`\-march=avx10.<N>\*(C'\fR enforce a vector
length
-restriction, i.e. despite these otherwise being "enabling" options, using
+suffixes permitted on \*(fC\*(C`\-march=avx10.<N>\*(C'\fR enforce a vector
length
+restriction, i.e.\& despite these otherwise being "enabling" options, using
these suffixes will disable all insns with wider vector or mask register
operands.
.Sp
-When the \f(CW\*(C`.arch\*(C'\fR directive is used with \fB\-march\fR, the
-\&\f(CW\*(C`.arch\*(C'\fR directive will take precedent.
+When the \*(fC\*(C`.arch\*(C'\fR directive is used with \fB\-march\fR, the
+\&\*(fC\*(C`.arch\*(C'\fR directive will take precedent.
.IP \fB\-mtune=\fR\fICPU\fR 4
.IX Item "-mtune=CPU"
This option specifies a processor to optimize for. When used in
@@ -1610,9 +1631,9 @@ for any SSE instruction.
.PD
These options control how the assembler should encode scalar AVX
instructions. \fB\-mavxscalar=\fR\fI128\fR will encode scalar
-AVX instructions with 128bit vector length, which is the default.
+AVX instructions with 128-bit vector length, which is the default.
\&\fB\-mavxscalar=\fR\fI256\fR will encode scalar AVX instructions
-with 256bit vector length.
+with 256-bit vector length.
.Sp
WARNING: Don't use this for production code \- due to CPU errata the
resulting code may not work on certain models.
@@ -1640,9 +1661,9 @@ resulting code may not work on certain m
.PD
These options control how the assembler should encode length-ignored
(LIG) EVEX instructions. \fB\-mevexlig=\fR\fI128\fR will encode LIG
-EVEX instructions with 128bit vector length, which is the default.
+EVEX instructions with 128-bit vector length, which is the default.
\&\fB\-mevexlig=\fR\fI256\fR and \fB\-mevexlig=\fR\fI512\fR will
-encode LIG EVEX instructions with 256bit and 512bit vector length,
+encode LIG EVEX instructions with 256-bit and 512-bit vector length,
respectively.
.IP \fB\-mevexwig=\fR\fI0\fR 4
.IX Item "-mevexwig=0"
@@ -1662,7 +1683,7 @@ evex.w = 1.
.IX Item "-mmnemonic=intel"
.PD
This option specifies instruction mnemonic for matching instructions.
-The \f(CW\*(C`.att_mnemonic\*(C'\fR and \f(CW\*(C`.intel_mnemonic\*(C'\fR
directives will
+The \*(fC\*(C`.att_mnemonic\*(C'\fR and \*(fC\*(C`.intel_mnemonic\*(C'\fR
directives will
take precedent.
.IP \fB\-msyntax=\fR\fIatt\fR 4
.IX Item "-msyntax=att"
@@ -1671,12 +1692,12 @@ take precedent.
.IX Item "-msyntax=intel"
.PD
This option specifies instruction syntax when processing instructions.
-The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR
directives will
+The \*(fC\*(C`.att_syntax\*(C'\fR and \*(fC\*(C`.intel_syntax\*(C'\fR
directives will
take precedent.
.IP \fB\-mnaked\-reg\fR 4
.IX Item "-mnaked-reg"
This option specifies that registers don't require a \fB%\fR prefix.
-The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR
directives will take precedent.
+The \*(fC\*(C`.att_syntax\*(C'\fR and \*(fC\*(C`.intel_syntax\*(C'\fR
directives will take precedent.
.IP \fB\-madd\-bnd\-prefix\fR 4
.IX Item "-madd-bnd-prefix"
This option forces the assembler to add BND prefix to all branches, even
@@ -1693,7 +1714,7 @@ instructions.
.IP \fB\-mbig\-obj\fR 4
.IX Item "-mbig-obj"
On PE/COFF target this option forces the use of big object file
-format, which allows more than 32768 sections.
+format, which allows more than 32,768 sections.
.IP \fB\-momit\-lock\-prefix=\fR\fIno\fR 4
.IX Item "-momit-lock-prefix=no"
.PD 0
@@ -1823,7 +1844,7 @@ after loading branch target register.
.PD
These options control whether the assembler should generate lfence
before ret. \fB\-mlfence\-before\-ret=\fR\fIor\fR will generate
-generate or instruction with lfence.
+or instruction with lfence.
\&\fB\-mlfence\-before\-ret=\fR\fIshl/yes\fR will generate shl instruction
with lfence. \fB\-mlfence\-before\-ret=\fR\fInot\fR will generate not
instruction with lfence. \fB\-mlfence\-before\-ret=\fR\fInone\fR will not
@@ -1998,7 +2019,7 @@ PRU processor.
.IX Item "-mlink-relax"
Assume that LD would optimize LDI32 instructions by checking the upper
16 bits of the \fIexpression\fR. If they are all zeros, then LD would
-shorten the LDI32 instruction to a single LDI. In such case
\f(CW\*(C`as\*(C'\fR
+shorten the LDI32 instruction to a single LDI. In such case
\*(fC\*(C`as\*(C'\fR
will output DIFF relocations for diff expressions.
.IP \fB\-mno\-link\-relax\fR 4
.IX Item "-mno-link-relax"
@@ -2015,7 +2036,7 @@ a MIPS processor.
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
This option sets the largest size of an object that can be referenced
-implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for
targets that
+implicitly with the \*(fC\*(C`gp\*(C'\fR register. It is only accepted for
targets that
use ECOFF format, such as a DECstation running Ultrix. The default value is 8.
.IP \fB\-EB\fR 4
.IX Item "-EB"
@@ -2095,7 +2116,7 @@ followed by a load instruction.
.PD
Do not attempt to schedule the preceding instruction into the delay slot
of a branch instruction placed at the end of a short loop of six
-instructions or fewer and always schedule a \f(CW\*(C`nop\*(C'\fR instruction
there
+instructions or fewer and always schedule a \*(fC\*(C`nop\*(C'\fR instruction
there
instead. The short loop bug under certain conditions causes loops to
execute only once or twice, due to a hardware bug in the R5900 chip.
.IP \fB\-mdebug\fR 4
@@ -2112,7 +2133,7 @@ section instead of the standard ELF .sta
.IP \fB\-mno\-pdr\fR 4
.IX Item "-mno-pdr"
.PD
-Control generation of \f(CW\*(C`.pdr\*(C'\fR sections.
+Control generation of \*(fC\*(C`.pdr\*(C'\fR sections.
.IP \fB\-mgp32\fR 4
.IX Item "-mgp32"
.PD 0
@@ -2155,7 +2176,7 @@ registers when supported by the ISA. \f
.IX Item "-no-mips16"
.PD
Generate code for the MIPS 16 processor. This is equivalent to putting
-\&\f(CW\*(C`.module mips16\*(C'\fR at the start of the assembly file.
\fB\-no\-mips16\fR
+\&\*(fC\*(C`.module mips16\*(C'\fR at the start of the assembly file.
\fB\-no\-mips16\fR
turns off this option.
.IP \fB\-mmips16e2\fR 4
.IX Item "-mmips16e2"
@@ -2164,7 +2185,7 @@ turns off this option.
.IX Item "-mno-mips16e2"
.PD
Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent
-to putting \f(CW\*(C`.module mips16e2\*(C'\fR at the start of the assembly
file.
+to putting \*(fC\*(C`.module mips16e2\*(C'\fR at the start of the assembly
file.
\&\fB\-mno\-mips16e2\fR turns off this option.
.IP \fB\-mmicromips\fR 4
.IX Item "-mmicromips"
@@ -2173,9 +2194,9 @@ to putting \f(CW\*(C`.module mips16e2\*(
.IX Item "-mno-micromips"
.PD
Generate code for the microMIPS processor. This is equivalent to putting
-\&\f(CW\*(C`.module micromips\*(C'\fR at the start of the assembly file.
+\&\*(fC\*(C`.module micromips\*(C'\fR at the start of the assembly file.
\&\fB\-mno\-micromips\fR turns off this option. This is equivalent to putting
-\&\f(CW\*(C`.module nomicromips\*(C'\fR at the start of the assembly file.
+\&\*(fC\*(C`.module nomicromips\*(C'\fR at the start of the assembly file.
.IP \fB\-msmartmips\fR 4
.IX Item "-msmartmips"
.PD 0
@@ -2183,7 +2204,7 @@ Generate code for the microMIPS processo
.IX Item "-mno-smartmips"
.PD
Enables the SmartMIPS extension to the MIPS32 instruction set. This is
-equivalent to putting \f(CW\*(C`.module smartmips\*(C'\fR at the start of the
assembly
+equivalent to putting \*(fC\*(C`.module smartmips\*(C'\fR at the start of the
assembly
file. \fB\-mno\-smartmips\fR turns off this option.
.IP \fB\-mips3d\fR 4
.IX Item "-mips3d"
@@ -2332,9 +2353,9 @@ This tells the assembler to accept Loong
.PD
Only use 32\-bit instruction encodings when generating code for the
microMIPS processor. This option inhibits the use of any 16\-bit
-instructions. This is equivalent to putting \f(CW\*(C`.set insn32\*(C'\fR at
+instructions. This is equivalent to putting \*(fC\*(C`.set insn32\*(C'\fR at
the start of the assembly file. \fB\-mno\-insn32\fR turns off this
-option. This is equivalent to putting \f(CW\*(C`.set noinsn32\*(C'\fR at the
+option. This is equivalent to putting \*(fC\*(C`.set noinsn32\*(C'\fR at the
start of the assembly file. By default \fB\-mno\-insn32\fR is
selected, allowing all instructions to be used.
.IP \fB\-\-construct\-floats\fR 4
@@ -2427,19 +2448,19 @@ Don't generate position-independent code
The following options are available when as is configured for a
Meta processor.
.ie n .IP """\-mcpu=metac11""" 4
-.el .IP \f(CW\-mcpu=metac11\fR 4
+.el .IP \*(fC\-mcpu=metac11\fR 4
.IX Item "-mcpu=metac11"
Generate code for Meta 1.1.
.ie n .IP """\-mcpu=metac12""" 4
-.el .IP \f(CW\-mcpu=metac12\fR 4
+.el .IP \*(fC\-mcpu=metac12\fR 4
.IX Item "-mcpu=metac12"
Generate code for Meta 1.2.
.ie n .IP """\-mcpu=metac21""" 4
-.el .IP \f(CW\-mcpu=metac21\fR 4
+.el .IP \*(fC\-mcpu=metac21\fR 4
.IX Item "-mcpu=metac21"
Generate code for Meta 2.1.
.ie n .IP """\-mfpu=metac21""" 4
-.el .IP \f(CW\-mfpu=metac21\fR 4
+.el .IP \*(fC\-mfpu=metac21\fR 4
.IX Item "-mfpu=metac21"
Allow code to use FPU hardware of Meta 2.1.
.PP
@@ -2448,122 +2469,120 @@ See the info pages for documentation of
The following options are available when as is configured for a
NDS32 processor.
.ie n .IP """\-O1""" 4
-.el .IP \f(CW\-O1\fR 4
+.el .IP \*(fC\-O1\fR 4
.IX Item "-O1"
Optimize for performance.
.ie n .IP """\-Os""" 4
-.el .IP \f(CW\-Os\fR 4
+.el .IP \*(fC\-Os\fR 4
.IX Item "-Os"
Optimize for space.
.ie n .IP """\-EL""" 4
-.el .IP \f(CW\-EL\fR 4
+.el .IP \*(fC\-EL\fR 4
.IX Item "-EL"
Produce little endian data output.
.ie n .IP """\-EB""" 4
-.el .IP \f(CW\-EB\fR 4
+.el .IP \*(fC\-EB\fR 4
.IX Item "-EB"
Produce little endian data output.
.ie n .IP """\-mpic""" 4
-.el .IP \f(CW\-mpic\fR 4
+.el .IP \*(fC\-mpic\fR 4
.IX Item "-mpic"
Generate PIC.
.ie n .IP """\-mno\-fp\-as\-gp\-relax""" 4
-.el .IP \f(CW\-mno\-fp\-as\-gp\-relax\fR 4
+.el .IP \*(fC\-mno\-fp\-as\-gp\-relax\fR 4
.IX Item "-mno-fp-as-gp-relax"
Suppress fp-as-gp relaxation for this file.
.ie n .IP """\-mb2bb\-relax""" 4
-.el .IP \f(CW\-mb2bb\-relax\fR 4
+.el .IP \*(fC\-mb2bb\-relax\fR 4
.IX Item "-mb2bb-relax"
Back-to-back branch optimization.
.ie n .IP """\-mno\-all\-relax""" 4
-.el .IP \f(CW\-mno\-all\-relax\fR 4
+.el .IP \*(fC\-mno\-all\-relax\fR 4
.IX Item "-mno-all-relax"
Suppress all relaxation for this file.
.ie n .IP """\-march=<arch name>""" 4
-.el .IP "\f(CW\-march=<arch name>\fR" 4
+.el .IP "\*(fC\-march=<arch name>\fR" 4
.IX Item "-march=<arch name>"
Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f,
v3s, v2, v2j, v2f, v2s.
.ie n .IP """\-mbaseline=<baseline>""" 4
-.el .IP \f(CW\-mbaseline=<baseline>\fR 4
+.el .IP \*(fC\-mbaseline=<baseline>\fR 4
.IX Item "-mbaseline=<baseline>"
Assemble for baseline <baseline> which could be v2, v3, v3m.
.ie n .IP """\-mfpu\-freg=\fIFREG\fR""" 4
-.el .IP \f(CW\-mfpu\-freg=\fR\f(CIFREG\fR\f(CW\fR 4
+.el .IP \*(fC\-mfpu\-freg=\fR\f(CIFREG\fR\*(fC\fR 4
.IX Item "-mfpu-freg=FREG"
Specify a FPU configuration.
.RS 4
.ie n .IP """0 8 SP / 4 DP registers""" 4
-.el .IP "\f(CW0 8 SP / 4 DP registers\fR" 4
+.el .IP "\*(fC0 8 SP / 4 DP registers\fR" 4
.IX Item "0 8 SP / 4 DP registers"
.PD 0
.ie n .IP """1 16 SP / 8 DP registers""" 4
-.el .IP "\f(CW1 16 SP / 8 DP registers\fR" 4
+.el .IP "\*(fC1 16 SP / 8 DP registers\fR" 4
.IX Item "1 16 SP / 8 DP registers"
.ie n .IP """2 32 SP / 16 DP registers""" 4
-.el .IP "\f(CW2 32 SP / 16 DP registers\fR" 4
+.el .IP "\*(fC2 32 SP / 16 DP registers\fR" 4
.IX Item "2 32 SP / 16 DP registers"
.ie n .IP """3 32 SP / 32 DP registers""" 4
-.el .IP "\f(CW3 32 SP / 32 DP registers\fR" 4
+.el .IP "\*(fC3 32 SP / 32 DP registers\fR" 4
.IX Item "3 32 SP / 32 DP registers"
.RE
-.RS 4
-.RE
.ie n .IP """\-mabi=\fIabi\fR""" 4
-.el .IP \f(CW\-mabi=\fR\f(CIabi\fR\f(CW\fR 4
+.el .IP \*(fC\-mabi=\fR\f(CIabi\fR\*(fC\fR 4
.IX Item "-mabi=abi"
.PD
Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
.ie n .IP """\-m[no\-]mac""" 4
-.el .IP \f(CW\-m[no\-]mac\fR 4
+.el .IP \*(fC\-m[no\-]mac\fR 4
.IX Item "-m[no-]mac"
Enable/Disable Multiply instructions support.
.ie n .IP """\-m[no\-]div""" 4
-.el .IP \f(CW\-m[no\-]div\fR 4
+.el .IP \*(fC\-m[no\-]div\fR 4
.IX Item "-m[no-]div"
Enable/Disable Divide instructions support.
.ie n .IP """\-m[no\-]16bit\-ext""" 4
-.el .IP \f(CW\-m[no\-]16bit\-ext\fR 4
+.el .IP \*(fC\-m[no\-]16bit\-ext\fR 4
.IX Item "-m[no-]16bit-ext"
Enable/Disable 16\-bit extension
.ie n .IP """\-m[no\-]dx\-regs""" 4
-.el .IP \f(CW\-m[no\-]dx\-regs\fR 4
+.el .IP \*(fC\-m[no\-]dx\-regs\fR 4
.IX Item "-m[no-]dx-regs"
Enable/Disable d0/d1 registers
.ie n .IP """\-m[no\-]perf\-ext""" 4
-.el .IP \f(CW\-m[no\-]perf\-ext\fR 4
+.el .IP \*(fC\-m[no\-]perf\-ext\fR 4
.IX Item "-m[no-]perf-ext"
Enable/Disable Performance extension
.ie n .IP """\-m[no\-]perf2\-ext""" 4
-.el .IP \f(CW\-m[no\-]perf2\-ext\fR 4
+.el .IP \*(fC\-m[no\-]perf2\-ext\fR 4
.IX Item "-m[no-]perf2-ext"
Enable/Disable Performance extension 2
.ie n .IP """\-m[no\-]string\-ext""" 4
-.el .IP \f(CW\-m[no\-]string\-ext\fR 4
+.el .IP \*(fC\-m[no\-]string\-ext\fR 4
.IX Item "-m[no-]string-ext"
Enable/Disable String extension
.ie n .IP """\-m[no\-]reduced\-regs""" 4
-.el .IP \f(CW\-m[no\-]reduced\-regs\fR 4
+.el .IP \*(fC\-m[no\-]reduced\-regs\fR 4
.IX Item "-m[no-]reduced-regs"
Enable/Disable Reduced Register configuration (GPR16) option
.ie n .IP """\-m[no\-]audio\-isa\-ext""" 4
-.el .IP \f(CW\-m[no\-]audio\-isa\-ext\fR 4
+.el .IP \*(fC\-m[no\-]audio\-isa\-ext\fR 4
.IX Item "-m[no-]audio-isa-ext"
Enable/Disable AUDIO ISA extension
.ie n .IP """\-m[no\-]fpu\-sp\-ext""" 4
-.el .IP \f(CW\-m[no\-]fpu\-sp\-ext\fR 4
+.el .IP \*(fC\-m[no\-]fpu\-sp\-ext\fR 4
.IX Item "-m[no-]fpu-sp-ext"
Enable/Disable FPU SP extension
.ie n .IP """\-m[no\-]fpu\-dp\-ext""" 4
-.el .IP \f(CW\-m[no\-]fpu\-dp\-ext\fR 4
+.el .IP \*(fC\-m[no\-]fpu\-dp\-ext\fR 4
.IX Item "-m[no-]fpu-dp-ext"
Enable/Disable FPU DP extension
.ie n .IP """\-m[no\-]fpu\-fma""" 4
-.el .IP \f(CW\-m[no\-]fpu\-fma\fR 4
+.el .IP \*(fC\-m[no\-]fpu\-fma\fR 4
.IX Item "-m[no-]fpu-fma"
Enable/Disable FPU fused-multiply-add instructions
.ie n .IP """\-mall\-ext""" 4
-.el .IP \f(CW\-mall\-ext\fR 4
+.el .IP \*(fC\-mall\-ext\fR 4
.IX Item "-mall-ext"
Turn on all extensions and instructions support
.PP
@@ -2861,8 +2880,8 @@ Controls whether the assembler performs
a warning message in case of a mismatch with the operand register type.
The default (which can be restored by using the \fBrelaxed\fR argument) is
to perform relaxed register name type checks, which allow floating point
-register (FPR) names \f(CW%f0\fR to \f(CW%f15\fR to be specified as argument
to vector register
-(VR) operands and vector register (VR) names \f(CW%v0\fR to \f(CW%v15\fR to be
specified as
+register (FPR) names \*(fC%f0\fR to \*(fC%f15\fR to be specified as argument
to vector register
+(VR) operands and vector register (VR) names \*(fC%v0\fR to \*(fC%v15\fR to be
specified as
argument to floating point register (FPR) operands. This is acceptable as the
FPR are embedded into the lower half of the VR.
Using the \fBstrict\fR argument strict register name type checks are
@@ -2877,8 +2896,8 @@ TMS320C6000 processor.
Enable (only) instructions from architecture \fIarch\fR. By default,
all instructions are permitted.
.Sp
-The following values of \fIarch\fR are accepted: \f(CW\*(C`c62x\*(C'\fR,
-\&\f(CW\*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR,
\f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR.
+The following values of \fIarch\fR are accepted: \*(fC\*(C`c62x\*(C'\fR,
+\&\*(fC\*(C`c64x\*(C'\fR, \*(fC\*(C`c64x+\*(C'\fR, \*(fC\*(C`c67x\*(C'\fR,
\*(fC\*(C`c67x+\*(C'\fR, \*(fC\*(C`c674x\*(C'\fR.
.IP \fB\-mdsbt\fR 4
.IX Item "-mdsbt"
.PD 0
@@ -2886,7 +2905,7 @@ The following values of \fIarch\fR are a
.IX Item "-mno-dsbt"
.PD
The \fB\-mdsbt\fR option causes the assembler to generate the
-\&\f(CW\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that
the
+\&\*(fC\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that
the
code is using DSBT addressing. The \fB\-mno\-dsbt\fR option, the
default, causes the tag to have a value of 0, indicating that the code
does not use DSBT addressing. The linker will emit a warning if
@@ -2900,7 +2919,7 @@ objects of different type (DSBT and non-
.IX Item "-mpid=far"
.PD
The \fB\-mpid=\fR option causes the assembler to generate the
-\&\f(CW\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of
data
+\&\*(fC\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of
data
addressing used by the code. \fB\-mpid=no\fR, the default,
indicates position-dependent data addressing, \fB\-mpid=near\fR
indicates position-independent addressing with GOT accesses using near
@@ -2915,9 +2934,9 @@ are linked together.
.IX Item "-mno-pic"
.PD
The \fB\-mpic\fR option causes the assembler to generate the
-\&\f(CW\*(C`Tag_ABI_PIC\*(C'\fR attribute with a value of 1, indicating that
the
+\&\*(fC\*(C`Tag_ABI_PIC\*(C'\fR attribute with a value of 1, indicating that
the
code is using position-independent code addressing, The
-\&\f(CW\*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a
value of
+\&\*(fC\*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a
value of
0, indicating position-dependent code addressing. The linker will
emit a warning if objects of different type (position-dependent and
position-independent) are linked together.
@@ -2948,10 +2967,10 @@ assemble an instruction that will not ex
the assembler will issue an error message.
.Sp
The following names are recognized:
-\&\f(CW\*(C`mcm24\*(C'\fR
-\&\f(CW\*(C`mcm\*(C'\fR
-\&\f(CW\*(C`gr5\*(C'\fR
-\&\f(CW\*(C`gr6\*(C'\fR
+\&\*(fC\*(C`mcm24\*(C'\fR
+\&\*(fC\*(C`mcm\*(C'\fR
+\&\*(fC\*(C`gr5\*(C'\fR
+\&\*(fC\*(C`gr6\*(C'\fR
.PP
The following options are available when as is configured for an
Xtensa processor.
@@ -2964,11 +2983,11 @@ placed in a data RAM/ROM. With \fB\-\-t
literals are interspersed in the text section in order to keep them as
close as possible to their references. This may be necessary for large
assembly files, where the literals would otherwise be out of range of the
-\&\f(CW\*(C`L32R\*(C'\fR instructions in the text section. Literals are
grouped into
-pools following \f(CW\*(C`.literal_position\*(C'\fR directives or preceding
-\&\f(CW\*(C`ENTRY\*(C'\fR instructions. These options only affect literals
referenced
-via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for absolute mode
-\&\f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
+\&\*(fC\*(C`L32R\*(C'\fR instructions in the text section. Literals are
grouped into
+pools following \*(fC\*(C`.literal_position\*(C'\fR directives or preceding
+\&\*(fC\*(C`ENTRY\*(C'\fR instructions. These options only affect literals
referenced
+via PC-relative \*(fC\*(C`L32R\*(C'\fR instructions; literals for absolute mode
+\&\*(fC\*(C`L32R\*(C'\fR instructions are handled separately.
.IP "\fB\-\-auto\-litpools | \-\-no\-auto\-litpools\fR" 4
.IX Item "--auto-litpools | --no-auto-litpools"
Control the treatment of literal pools. The default is
@@ -2977,31 +2996,33 @@ Control the treatment of literal pools.
in the output file. This allows the literal pool to be placed in a data
RAM/ROM. With \fB\-\-auto\-litpools\fR, the literals are interspersed
in the text section in order to keep them as close as possible to their
-references, explicit \f(CW\*(C`.literal_position\*(C'\fR directives are not
+references, explicit \*(fC\*(C`.literal_position\*(C'\fR directives are not
required. This may be necessary for very large functions, where single
literal pool at the beginning of the function may not be reachable by
-\&\f(CW\*(C`L32R\*(C'\fR instructions at the end. These options only affect
-literals referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions;
literals
-for absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
+\&\*(fC\*(C`L32R\*(C'\fR instructions at the end. These options only affect
+literals referenced via PC-relative \*(fC\*(C`L32R\*(C'\fR instructions;
literals
+for absolute mode \*(fC\*(C`L32R\*(C'\fR instructions are handled separately.
When used together with \fB\-\-text\-section\-literals\fR,
\&\fB\-\-auto\-litpools\fR takes precedence.
.IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4
.IX Item "--absolute-literals | --no-absolute-literals"
-Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use
absolute
+Indicate to the assembler whether \*(fC\*(C`L32R\*(C'\fR instructions use
absolute
or PC-relative addressing. If the processor includes the absolute
-addressing option, the default is to use absolute \f(CW\*(C`L32R\*(C'\fR
-relocations. Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR
relocations
+addressing option, the default is to use absolute \*(fC\*(C`L32R\*(C'\fR
+relocations. Otherwise, only the PC-relative \*(fC\*(C`L32R\*(C'\fR
relocations
can be used.
.IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4
.IX Item "--target-align | --no-target-align"
Enable or disable automatic alignment to reduce branch penalties at some
-expense in code size. This optimization is enabled by default. Note
-that the assembler will always align instructions like \f(CW\*(C`LOOP\*(C'\fR
that
+expense in code size.
+This optimization is enabled by default. Note
+that the assembler will always align instructions like \*(fC\*(C`LOOP\*(C'\fR
that
have fixed alignment requirements.
.IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4
.IX Item "--longcalls | --no-longcalls"
Enable or disable transformation of call instructions to allow calls
-across a greater range of addresses. This option should be used when call
+across a greater range of addresses.
+This option should be used when call
targets can potentially be out of range. It may degrade both code size
and performance, but the linker can generally optimize away the
unnecessary overhead when a call ends up within range. The default is
@@ -3021,13 +3042,14 @@ multiple times to rename multiple sectio
.IP "\fB\-\-trampolines | \-\-no\-trampolines\fR" 4
.IX Item "--trampolines | --no-trampolines"
Enable or disable transformation of jump instructions to allow jumps
-across a greater range of addresses. This option should be used when jump
targets can
+across a greater range of addresses.
+This option should be used when jump targets can
potentially be out of range. In the absence of such jumps this option
does not affect code size or performance. The default is
\&\fB\-\-trampolines\fR.
.IP "\fB\-\-abi\-windowed | \-\-abi\-call0\fR" 4
.IX Item "--abi-windowed | --abi-call0"
-Choose ABI tag written to the \f(CW\*(C`.xtensa.info\*(C'\fR section. ABI tag
+Choose ABI tag written to the \*(fC\*(C`.xtensa.info\*(C'\fR section. ABI tag
indicates ABI of the assembly code. A warning is issued by the linker
on an attempt to link object files with inconsistent ABI tags.
Default ABI is chosen by the Xtensa core configuration.
@@ -3035,8 +3057,8 @@ Default ABI is chosen by the Xtensa core
The following options are available when as is configured for an
Z80 processor.
.PP
-\&\f(CW@chapter\fR Z80 Dependent Features
-.SS "Command-line Options"
+\&\*(fC@chapter\fR Z80 Dependent Features
+.SS Command-line Options
.IX Subsection "Command-line Options"
.IP \fB\-march=\fR\fICPU\fR\fB[\-\fR\fIEXT\fR\fB...][+\fR\fIEXT\fR\fB...]\fR 4
.IX Item "-march=CPU[-EXT...][+EXT...]"
@@ -3044,35 +3066,35 @@ This option specifies the target process
an error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names
are recognized:
-\&\f(CW\*(C`z80\*(C'\fR,
-\&\f(CW\*(C`z180\*(C'\fR,
-\&\f(CW\*(C`ez80\*(C'\fR,
-\&\f(CW\*(C`gbz80\*(C'\fR,
-\&\f(CW\*(C`z80n\*(C'\fR,
-\&\f(CW\*(C`r800\*(C'\fR.
+\&\*(fC\*(C`z80\*(C'\fR,
+\&\*(fC\*(C`z180\*(C'\fR,
+\&\*(fC\*(C`ez80\*(C'\fR,
+\&\*(fC\*(C`gbz80\*(C'\fR,
+\&\*(fC\*(C`z80n\*(C'\fR,
+\&\*(fC\*(C`r800\*(C'\fR.
In addition to the basic instruction set, the assembler can be told to
accept some extension mnemonics. For example,
-\&\f(CW\*(C`\-march=z180+sli+infc\*(C'\fR extends \fIz180\fR with \fISLI\fR
instructions and
+\&\*(fC\*(C`\-march=z180+sli+infc\*(C'\fR extends \fIz180\fR with \fISLI\fR
instructions and
\&\fIIN F,(C)\fR. The following extensions are currently supported:
-\&\f(CW\*(C`full\*(C'\fR (all known instructions),
-\&\f(CW\*(C`adl\*(C'\fR (ADL CPU mode by default, eZ80 only),
-\&\f(CW\*(C`sli\*(C'\fR (instruction known as \fISLI\fR, \fISLL\fR or
\fISL1\fR),
-\&\f(CW\*(C`xyhl\*(C'\fR (instructions with halves of index registers:
\fIIXL\fR, \fIIXH\fR,
+\&\*(fC\*(C`full\*(C'\fR (all known instructions),
+\&\*(fC\*(C`adl\*(C'\fR (ADL CPU mode by default, eZ80 only),
+\&\*(fC\*(C`sli\*(C'\fR (instruction known as \fISLI\fR, \fISLL\fR or
\fISL1\fR),
+\&\*(fC\*(C`xyhl\*(C'\fR (instructions with halves of index registers:
\fIIXL\fR, \fIIXH\fR,
\&\fIIYL\fR, \fIIYH\fR),
-\&\f(CW\*(C`xdcb\*(C'\fR (instructions like \fIRotOp (II+d),R\fR and \fIBitOp
n,(II+d),R\fR),
-\&\f(CW\*(C`infc\*(C'\fR (instruction \fIIN F,(C)\fR or \fIIN (C)\fR),
-\&\f(CW\*(C`outc0\*(C'\fR (instruction \fIOUT (C),0\fR).
+\&\*(fC\*(C`xdcb\*(C'\fR (instructions like \fIRotOp (II+d),R\fR and \fIBitOp
n,(II+d),R\fR),
+\&\*(fC\*(C`infc\*(C'\fR (instruction \fIIN F,(C)\fR or \fIIN (C)\fR),
+\&\*(fC\*(C`outc0\*(C'\fR (instruction \fIOUT (C),0\fR).
Note that rather than extending a basic instruction set, the extension
-mnemonics starting with \f(CW\*(C`\-\*(C'\fR revoke the respective
functionality:
-\&\f(CW\*(C`\-march=z80\-full+xyhl\*(C'\fR first removes all default
extensions and adds
+mnemonics starting with \*(fC\*(C`\-\*(C'\fR revoke the respective
functionality:
+\&\*(fC\*(C`\-march=z80\-full+xyhl\*(C'\fR first removes all default
extensions and adds
support for index registers halves only.
.Sp
-If this option is not specified then \f(CW\*(C`\-march=z80+xyhl+infc\*(C'\fR
is assumed.
+If this option is not specified then \*(fC\*(C`\-march=z80+xyhl+infc\*(C'\fR
is assumed.
.IP \fB\-local\-prefix=\fR\fIprefix\fR 4
.IX Item "-local-prefix=prefix"
Mark all labels with specified prefix as local. But such label can be
marked global explicitly in the code. This option do not change default
-local label prefix \f(CW\*(C`.L\*(C'\fR, it is just adds new one.
+local label prefix \*(fC\*(C`.L\*(C'\fR, it is just adds new one.
.IP \fB\-colonless\fR 4
.IX Item "-colonless"
Accept colonless labels. All symbols at line begin are treated as labels.
@@ -3085,12 +3107,12 @@ Single precision floating point numbers
.IP \fB\-fp\-d=\fR\fIFORMAT\fR 4
.IX Item "-fp-d=FORMAT"
Double precision floating point numbers format. Default: ieee754 (64 bit).
-.SH "SEE ALSO"
+.SH SEE ALSO
.IX Header "SEE ALSO"
\&\fBgcc\fR\|(1), \fBld\fR\|(1), and the Info entries for \fIbinutils\fR and
\fIld\fR.
.SH COPYRIGHT
.IX Header "COPYRIGHT"
-Copyright (c) 1991\-2025 Free Software Foundation, Inc.
+Copyright (c) 1991\(en2025 Free Software Foundation, Inc.
.PP
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
Any program (person), that produces man pages, should check the output
for defects by using (both groff and nroff)
[gn]roff -mandoc -t -ww -b -z -K utf8 <man page>
The same goes for man pages that are used as an input.
For a style guide use
mandoc -T lint
-.-
Any "autogenerator" should check its products with the above mentioned
'groff', 'mandoc', and additionally with 'nroff ...'.
It should also check its input files for too long (> 80) lines.
This is just a simple quality control measure.
The "autogenerator" may have to be corrected to get a better man page,
the source file may, and any additional file may.
Common defects:
Not removing trailing spaces (in in- and output).
The reason for these trailing spaces should be found and eliminated.
"git" has a "tool" to point out whitespace,
see for example "git-apply(1)" and git-config(1)")
Not beginning each input sentence on a new line.
Line length and patch size should thus be reduced.
The script "reportbug" uses 'quoted-printable' encoding when a line is
longer than 1024 characters in an 'ascii' file.
See man-pages(7), item "semantic newline".
-.-
The difference between the formatted output of the original and patched file
can be seen with:
nroff -mandoc <file1> > <out1>
nroff -mandoc <file2> > <out2>
diff -d -u <out1> <out2>
and for groff, using
\"printf '%s\n%s\n' '.kern 0' '.ss 12 0' | groff -mandoc -Z - \"
instead of 'nroff -mandoc'
Add the option '-t', if the file contains a table.
Read the output from 'diff -d -u ...' with 'less -R' or similar.
-.-.
If 'man' (man-db) is used to check the manual for warnings,
the following must be set:
The option \"-warnings=w\"
The environmental variable:
export MAN_KEEP_STDERR=yes (or any non-empty value)
or
(produce only warnings):
export MANROFFOPT=\"-ww -b -z\"
export MAN_KEEP_STDERR=yes (or any non-empty value)
-.-
