https://sourceware.org/bugzilla/show_bug.cgi?id=32036
--- Comment #3 from Sourceware Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Nelson Chu <nelsonc1...@sourceware.org>: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ca2590d7804b4ea563eec6f1127ed17a00c30315 commit ca2590d7804b4ea563eec6f1127ed17a00c30315 Author: Jiawei <jia...@iscas.ac.cn> Date: Tue Aug 20 10:10:21 2024 +0800 RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions. This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'. All disassemble instructions use the sreg format. Co-Authored by: Charlie Keaney <charlie.kea...@embecosm.com> Co-Authored by: Mary Bennett <mary.benn...@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamna...@embecosm.com> Co-Authored by: Sinan Lin <sinan....@linux.alibaba.com> Co-Authored by: Simon Cook <simon.c...@embecosm.com> Co-Authored by: Shihua Liao <shi...@iscas.ac.cn> Co-Authored by: Yulong Shi <yul...@iscas.ac.cn> gas/ChangeLog: PR 32036 * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-mv.d: New test. * testsuite/gas/riscv/zcmp-mv.s: New test. include/ChangeLog: PR 32036 * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode. (MASK_CM_MVA01S): New mask. (MATCH_CM_MVSA01): New opcode. (MASK_CM_MVSA01): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (OP_MASK_SREG1): New mask. (OP_SH_SREG1): New operand code. (OP_MASK_SREG2): New mask. (OP_SH_SREG2): New operand code. (X_A0): New reg number. (X_A1): Ditto. (X_S7): Ditto. (RISCV_SREG_0_7): New macro function. opcodes/ChangeLog: PR 32036 * riscv-dis.c (riscv_zcmp_get_sregno): New function. (print_insn_args): New operators. * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function. -- You are receiving this mail because: You are on the CC list for the bug.
