https://sourceware.org/bugzilla/show_bug.cgi?id=30449
--- Comment #2 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Nelson Chu <nelsonc1...@sourceware.org>: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ec2260af61501798d00e41c3180c63d25b11439c commit ec2260af61501798d00e41c3180c63d25b11439c Author: Jim Wilson <j...@sifive.com> Date: Thu Jun 1 12:10:16 2023 +0800 RISC-V: PR30449, Add lga assembler macro support. Originally discussion, https://github.com/riscv/riscv-isa-manual/pull/539 Added new load address pseudo instruction which is always expanded to GOT access, no matter the .option rvc is set or not. gas/ PR 30449 * config/tc-riscv.c (macro): Add M_LGA support. * testsuite/gas/riscv/la-variants.d: New. * testsuite/gas/riscv/la-variants.s: New. include/ PR 30449 * opcode/riscv.h (M_LGA): New. opcodes/ PR 30449 * riscv-opc.c (riscv_opcodes): Add lga support. -- You are receiving this mail because: You are on the CC list for the bug.
