https://sourceware.org/bugzilla/show_bug.cgi?id=22970
--- Comment #3 from Peter Smith <peter.smith at linaro dot org> ---
Hello Nick,
I've been able to try out the patch. It looks like it is doing what I'd expect
for the R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC relocation.
When I went back to the original LLVM patch, I tried the example and got a
missing relocation error. It looks like my PR was incomplete; I missed out:
R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
These correspond to the halfword, 32-bit and 64-bit word load instructions (the
LDST8 is the byte load instruction).
My apologies for missing these out, would it be possible to consider these as
well as they could be generated by a compiler with the same llvm patch?
An example to that can be assembled with clang --target=aarch64-linux-gnu
generates these relocations.
.text
.globl _start
.type _start, %function
_start: mrs x8, TPIDR_EL0
add x8, x8, :tprel_hi12:var0
ldr x0, [x8, :tprel_lo12_nc:var0]
add x8, x8, :tprel_hi12:var1
ldr w0, [x8, :tprel_lo12_nc:var1]
add x8, x8, :tprel_hi12:var2
ldrh w0, [x8, :tprel_lo12_nc:var2]
add x8, x8, :tprel_hi12:var3
ldrb w0, [x8, :tprel_lo12_nc:var3]
.globl var0
.globl var1
.globl var2
.globl var3
.type var0,@object
.type var1,@object
.type var2,@object
.type var3,@object
.section .tbss,"awT",@nobits
.p2align 2
var0:
.quad 0
.size var1, 8
var1:
.word 0
.size var1, 4
var2:
.hword 0
.size var2, 2
var3:
.byte 0
.size var3, 1
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