Hi Clive,
I think that there's a bug in the generation of ARM vmsr instructions
For future reference, it helps if you can open a bug report for problems
like this. You can use the bugzilla system here to do this:
http://sourceware.org/bugzilla/
in binutils 2.2.
I assume that you mean 2.22. Version 2.2 is *really* old...
vmsr fpexc, r0
I think this is a bug, unless there's some reason for disallowing fpsid& fpexc
that I haven't found....
No. It was just a snafu - the assembler was only supporting the normal
mode version of the VMSR instruction, not the priviledged mode versions
of it.
I am going to apply the patch below to fix this problem, and a similar
one for the VMRS instruction.
Cheers
Nick
gas/ChangeLog
2012-03-20 Nick Clifton <ni...@redhat.com>
* config/tc-arm.c (do_vmrs): Accept priviledged mode VFP system
registers.
(do_vmsr): Likewise.
(arm_opcode_insns): Do not default to using the FPSCR register in
the VMRS and VMSR registers.
gas/testsuite/ChangeLog
2012-03-20 Nick Clifton <ni...@redhat.com>
* gas/arm/vfp1xD.s: Add tests of the VMSR ad VMRS instructions in
priviledged modes.
* gas/arm/vfp1xD.d: Update expected output.
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.515
diff -u -3 -p -r1.515 tc-arm.c
--- gas/config/tc-arm.c 16 Mar 2012 14:00:35 -0000 1.515
+++ gas/config/tc-arm.c 20 Mar 2012 11:47:35 -0000
@@ -8102,8 +8102,18 @@ do_vmrs (void)
return;
}
- if (inst.operands[1].reg != 1)
- first_error (_("operand 1 must be FPSCR"));
+ switch (inst.operands[1].reg)
+ {
+ case 0: /* FPSID */
+ case 1: /* FPSCR */
+ case 6: /* MVFR1 */
+ case 7: /* MVFR0 */
+ case 8: /* FPEXC */
+ inst.instruction |= (inst.operands[1].reg << 16);
+ break;
+ default:
+ first_error (_("operand 1 must be a VFP extension System Register"));
+ }
inst.instruction |= (Rt << 12);
}
@@ -8121,8 +8131,16 @@ do_vmsr (void)
return;
}
- if (inst.operands[0].reg != 1)
- first_error (_("operand 0 must be FPSCR"));
+ switch (inst.operands[0].reg)
+ {
+ case 0: /* FPSID */
+ case 1: /* FPSCR */
+ case 8: /* FPEXC */
+ inst.instruction |= (inst.operands[0].reg << 16);
+ break;
+ default:
+ first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
+ }
inst.instruction |= (Rt << 12);
}
@@ -18147,8 +18165,8 @@ static const struct asm_opcode insns[] =
cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
cCE("fmstat", ef1fa10, 0, (), noargs),
- cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
- cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
+ cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
+ cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
Index: gas/testsuite/gas/arm/vfp1xD.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/vfp1xD.d,v
retrieving revision 1.11
diff -u -3 -p -r1.11 vfp1xD.d
--- gas/testsuite/gas/arm/vfp1xD.d 16 Nov 2009 11:47:36 -0000 1.11
+++ gas/testsuite/gas/arm/vfp1xD.d 20 Mar 2012 11:47:35 -0000
@@ -278,5 +278,12 @@ Disassembly of section .text:
0+430 <[^>]*> eee1ba10 vmsr fpscr, fp
0+434 <[^>]*> eee1ca10 vmsr fpscr, ip
0+438 <[^>]*> eee1ea10 vmsr fpscr, lr
-0+43c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-
+0+43c <[^>]*> eee01a10 vmsr fpsid, r1
+0+440 <[^>]*> eee82a10 vmsr fpexc, r2
+0+444 <[^>]*> eef03a10 vmrs r3, fpsid
+0+448 <[^>]*> eef64a10 vmrs r4, mvfr1
+0+44c <[^>]*> eef75a10 vmrs r5, mvfr0
+0+450 <[^>]*> eef86a10 vmrs r6, fpexc
+0+454 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+458 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+45c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
Index: gas/testsuite/gas/arm/vfp1xD.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/vfp1xD.s,v
retrieving revision 1.3
diff -u -3 -p -r1.3 vfp1xD.s
--- gas/testsuite/gas/arm/vfp1xD.s 16 Nov 2009 11:47:36 -0000 1.3
+++ gas/testsuite/gas/arm/vfp1xD.s 20 Mar 2012 11:47:35 -0000
@@ -381,4 +381,14 @@ F:
vmsr FPSCR, r12
vmsr FPSCR, r14
+ @ Priviledged externsions to VMSR/VMRS instructions
+ vmsr FPSID, r1
+ vmsr FPEXC, r2
+ vmrs r3, FPSID
+ vmrs r4, MVFR1
+ vmrs r5, MVFR0
+ vmrs r6, FPEXC
+
+ nop
+ nop
nop
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