When binutils-2.18 are configured with option
--target=arm-unknown-elf,
gcc-2.95.3 doesn't compile gas/config/tc-arm.c.
The first complain is in do_neon_cvt():
two variables are defined in an improper place.
I think they would better go to the begin of their block.
The second is in do_neon_ext(): the compiler tells of comparing
of signed and unsigned integers; it treats this as an error.
I suggest an explicit conversion to unsigned.
Best regards and a patch against the current CVS are attached.
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Index: tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.352
diff -U4 -r1.352 tc-arm.c
--- tc-arm.c 9 Mar 2008 15:20:31 -0000 1.352
+++ tc-arm.c 27 Mar 2008 06:11:34 -0000
@@ -12717,17 +12717,19 @@
{
case NS_DDI:
case NS_QQI:
{
+ unsigned immbits;
+ unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
+
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
return;
/* Fixed-point conversion with #0 immediate is encoded as an
integer conversion. */
if (inst.operands[2].present && inst.operands[2].imm == 0)
goto int_encode;
- unsigned immbits = 32 - inst.operands[2].imm;
- unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
+ immbits = 32 - inst.operands[2].imm;
inst.instruction = NEON_ENC_IMMED (inst.instruction);
if (flavour != -1)
inst.instruction |= enctab[flavour];
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
@@ -12960,9 +12962,10 @@
enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
struct neon_type_el et = neon_check_type (3, rs,
N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
unsigned imm = (inst.operands[3].imm * et.size) / 8;
- constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));
+ constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
+ _("shift out of range"));
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
inst.instruction |= HI1 (inst.operands[1].reg) << 7;
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