(+ Grant, Francois)
On Thu, 20 Aug 2020 at 02:04, Atish Patra <[email protected]> wrote: > > Hi All, > We are interested in adopting EBBR as the boot specification for the > embedded RISC-V platforms. > We firmly believe that EBBR is a very well defined specification for > boot requirement and there > is no need for reinventing the wheel for RISC-V. Hence, this is a > thread to discuss all the requirements > for adding RISC-V to EBBR. Here is my current understanding. Please > correct me if I am wrong. > > Logistic Requirement: > 1. As per the contribution guidelines[1], patches should be sent to > [email protected]. > and the specification will be hosted under "ARM-software" Github. > I am hoping that introducing RISC-V > related changes are okay with the current maintainers. > 2. The specification is licensed under Creative Commons. The RISC-V > related changes will refer to > some of the RISC-V specifications as well. AFAIK, there shouldn't > be an issue with that. > 3. It should be okay to add other copyrights in addition to "Arm > Limited and Contributors". > > Technical Requirement: > 1. Software status: > a. UEFI support for RISC-V Linux kernel is already available in > the mailing list[2]. The targeted upstream > merge is the 5.10 merge window. > b. U-Boot already supports UEFI for RISC-V. > c. EDK2 upstreaming is currently under progress [3] as well. > > Is it okay to start sending patches for EBBR RISC-V related changes > now or do we need to wait for EDK2 and Linux > kernel patches to be available upstream ? > > 2. RISC-V related sections in EBBR > a. UEFI: > Currently, RISC-V doesn't support a EFI_RESET_SYSTEM boot > service as firmware doesn't have a standard way > to reset the system. There is a proposal to add a system reset > function to Supervisor Binary Specification(SBI) which > can be mapped to EFI_RESET_SYSTEM by the firmware. Apart from > that, I believe RISC-V supports all UEFI boot and > run time services mandated by EBBR. Is it a blocker for RISC-V > EBBR compatibility? > b. RISC-V Multiprocessor Startup Protocol: This section will > contain the details of booting protocol for RISC-V and mandatory > RISC-V specifications that need to be implemented. > c. Firmware Storage: AFAIK, RISC-V platforms are already > compatible with this. > > Please let me know if I missed something or oversimplified any > requirement. We want to make RISC-V compatible with EBBR > sooner than later and ready work on any missing pieces if any. > > [1] https://github.com/ARM-software/ebbr/blob/master/CONTRIBUTING.rst > [2] https://lkml.org/lkml/2020/8/19/1252 > [3] > https://edk2.groups.io/g/devel/message/63831?p=,,,20,0,0,0::Created,,RISC-V,20,2,0,76053051 > [4] > https://lists.riscv.org/g/tech-unixplatformspec/message/49?p=,,,20,0,0,0::relevance,,Add+system+reset+extension,20,2,0,73235534 > > -- > Regards, > Atish _______________________________________________ boot-architecture mailing list [email protected] https://lists.linaro.org/mailman/listinfo/boot-architecture
