Hi all,
I am still trying to find a suitable way to split up a file. I have
attached a sample file for your viewing pleasure. This file is a standard
text file that I need to work on.
Here is the basic idea of what I'm trying to do.
1. I ONLY want to work on the area from *DESCRIPTION to *ENDS. Everything
else is irrelavant, but needed in the final document.
2. Comments (";") should be ignored but carried with the document.
3. I want to be able to do an enhanced search and replace, where if you
don't find it, add in the line. For example in the test file, there is a line
OUTLIB = lvsout
replace this with OUTLIB = TEST. Now if you don't find it add in (just
before the *ENDS) OUTLIB = TEST
I don't know how to do this nicely. For 1. do I read in the document as a
whole or split it with \n^*\w (look for a newline with a * at the beginning
of a line - my regex is probably hosed..), And if I do this how do I keep the
comments?
How do I ignore the comments period if I split this up?
For number 3 I can't come up with a way to look in a section and if you don't
find it, add it to the end? I am clueless here.
Any help would be greatly appreciated.
Thanks so much
--
Steven M. Klass
Physical Design Manager
National Semiconductor Corp
15210 S. 50th Street
Suite 120, Mail Stop AZ4
Phoenix, AZ 85044
Ph:480-629-2503
Fax:480-629-2476
[EMAIL PROTECTED]
http://www.nsc.com
; Process : Standard LVS (common to all processes to date)
; : Compares Layout to an Hspice Schematic Netlist
; : Manditory for tape out
;
; Document # :
; (this may mess up older designs)
;
*DESCRIPTION
MINI-SUMMARY = NO
;INDISK = xxx.gds ; Database file to check ;input from drac prog
;PRIMARY = xxx_top ; Topcell to be checked ;input from drac prog
OUTLIB = lvsout ; Topcell for error flags
OUTDISK = lvsout.gds ; File name of error database
PRINTFILE = lvsprt ; Job name, print&log file names
LISTERROR = 100 ; Max # of errors listed per check
SCALE = .001 MICRON ; user units / GDS II DB unit
RESOLUTION = .001 MICRON ; Snapping grid
SYSTEM = GDS2 ; Data Base format
MODE = EXEC NOW ; Execution mode
FLAG-ACUTEANGLE = YES ; Print acute angles
FLAG-OFFGRID = YES ; Print geometries off-grid
FLAGNON45 = YES ; Print NON-45 degree lines
FLAG-SELFINTERS = YES ; Print self intersecting polygons
KEEPDATA = SMART ; Don't keep intermediate files
SCHEMATIC = LVSLOGIC.DAT ; Compiled Schematic
FIX-INPUT-ORDER = YES ; Don't swap logic inputs
;OUTPUT-ONE-LAYER= YES ; Put error layers on on layer
;TEXT-PRI-ONLY = YES ; Text only top level ;input from drac prog
;DELCEL = TESTCELL ; Cell to exclude from LVS - USE CAUTION !!
DELCEL = DROPIN ; Cell to exclude from LVS - USE CAUTION !!
;
*END
;
*INPUT-LAYER
;
ANWI = 1 ; N Well Implant
TOX = 2 ; Thin OXide
APOL = 4 TEXT 4 ATTACH = POL ; POLy
PPI = 5 ; P Plus Implant
CON = 7 ; CONtact
ME1 = 8 TEXT 8 ATTACH = ME1 ; MEtal 1
VIA = 9 ; VIA
ME2 = 10 TEXT 10 ATTACH = ME2 ; MEtal 2
PAS = 11 ; PASsivation
VA2 = 12 ; ViA 2
ME3 = 13 TEXT 13 ATTACH = ME3 ; MEtal 3
BMP = 15
BJT = 30 ; Bipolar recognition layer
RES = 31 ; Resistor recognition layer
DIO = 32 ; Diode recognition layer
LDD = 33 ; HV Nmos recognition layer
;
SUBSTRATE = PSUB 60
CONNECT-LAYER = PSUB NWI PSD NSD WNSD POL ME1 ME2 ME3
;
*END
;
*OPERATION
;
NOT PSUB ANWI PWI ; Pwell
NOT PSUB PPI NPI ; N+ Implant
;
AND TOX PPI PDIF ; P+ Diffusion
AND TOX NPI NDIF ; N+ Diffusion
;
AND APOL RES PORES ; Poly resistor region
NOT APOL PORES POL ; All Poly except resistors
;
NOT RES PORES RES1 ; Resid not over poly
;
AND ANWI RES1 NWRES ; Nwell resistors
NOT ANWI NWRES NWI ; All Nwell except resistors
;
AND POL PDIF PGAT ; P+ Gate
NOT PDIF PGAT PSD0 ; All P+ Excluding Gates
;
AND PSD0 RES PPRES ; P+ resistors
NOT PSD0 PPRES PSD ; P+ S/D and taps
;
AND POL NDIF NGAT0 ; N+ Gate
NOT NDIF NGAT0 ANSD ; All N+ Excluding Gates
;
AND ANSD RES NPRES ; N+ resistors
NOT ANSD NPRES NSD0 ; All N+ except resistors
;
AND NSD0 LDD WNSD ; LDD S/D
NOT NSD0 WNSD NSD ; N+ S/D and taps
;
AND NGAT0 LDD WNGAT
NOT NGAT0 WNGAT NGAT
;
AND PSD PWI SUBTIE ; Substrate tie
AND NSD NWI WELTIE ; Nwell tie
;
CONNECT ME1 PSD BY CON
CONNECT ME1 NSD BY CON
CONNECT ME1 WNSD BY CON
CONNECT ME1 POL BY CON
CONNECT ME2 ME1 BY VIA
CONNECT ME3 ME2 BY VA2
CONNECT PSD PSUB BY SUBTIE
CONNECT NSD NWI BY WELTIE
;
ELEMENT RES[PO] PORES POL ; Poly Resistors
;PARAMETER RES[PO] 10 ; Value checking (LG Value)
;PARAMETER RES[PO] 14.5 ; Value checking (OKI Value)
;PARAMETER RES[PO] 35 ; Value checking (NAT Value)
PARAMETER RES[PO] 8 ; Value checking (SHP Value)
ELEMENT RES[NW] NWRES NWI ; Nwell Resistors
;PARAMETER RES[NW] 630 ; Value checking (LG Value)
;PARAMETER RES[NW] 1010 ; Value checking (OKI Value)
;PARAMETER RES[NW] 1595 ; Value checking (NAT Value)
PARAMETER RES[NW] 1200 ; Value checking (SHP Value)
ELEMENT RES[NP] NPRES NSD ; Nplus Resistors
;PARAMETER RES[NP] 75 ; Value checking (LG Value)
;PARAMETER RES[NP] 115 ; Value checking (OKI Value)
;PARAMETER RES[NP] 65 ; Value checking (NAT Value)
PARAMETER RES[NP] 90 ; Value checking (SHP Value)
ELEMENT RES[PP] PPRES PSD ; Pplus Resistors
;PARAMETER RES[PP] 105 ; Value checking (LG Value)
;PARAMETER RES[PP] 230 ; Value checking (OKI Value)
;PARAMETER RES[PP] 115 ; Value checking (NAT Value)
PARAMETER RES[PP] 120 ; Value checking (SHP Value)
;
ELEMENT BJT[PV] BJT PSUB NSD PSD ; Verticle PNP
;
ELEMENT DIO[N] DIO PSUB NSD ; Nplus Diode to Substrate
;
ELEMENT MOS[MP] PGAT POL PSD NWI ; Pmos Devices
ELEMENT MOS[MN] NGAT POL NSD PSUB ; Nmos Devices
;
ELEMENT LDD[N] WNGAT POL WNSD NSD PSUB ; Nmos LDD device
;
MULTILAB OUTPUT SHORT 50 ; Plot shorts
SAMELAB OUTPUT OPENS 50 ; Plot opens
;
;LVSCHK PRINTLINE=10000 RESVAL=10 WPERCENT=5 LPERCENT=0 MOSCAP-AREA=5
;LVSCHK PRINTLINE=500 WPERCENT=5 LPERCENT=0 MOSCAP-AREA=5
LVSCHK PRINTLINE=10000
;
;Uncomment the following for debugging a real nasty run
;
LVSPLOT NODE TYPE 1 OUTPUT NOD01 50 ; mtch nod to no dev
LVSPLOT NODE TYPE 2 OUTPUT NOD02 50 ; mtch dev to unmtch nod
LVSPLOT MOS TYPE 2 OUTPUT MOS02 50 ;
LVSPLOT NODE TYPE 3 OUTPUT NOD03 50 ; inconsistant mtch dev
LVSPLOT MOS TYPE 3 OUTPUT MOS03 50 ;
LVSPLOT NODE TYPE 4 OUTPUT NOD04 50 ; mtch nod to extra lay dev
LVSPLOT MOS TYPE 4 OUTPUT MOS04 50 ;
LVSPLOT NODE TYPE 5 OUTPUT NOD05 50 ; mtch nod to extra sch dev
LVSPLOT NODE TYPE 6 OUTPUT NOD06 50 ; mtch nod to unmtch lay and sch
LVSPLOT MOS TYPE 6 OUTPUT MOS06 50 ;
LVSPLOT MOS TYPE 7 OUTPUT MOS07 50 ; other unmtch lay
LVSPLOT MOS TYPE 9 OUTPUT MOS09 50 ; dev subtype mismatch
LVSPLOT MOS TYPE 11 OUTPUT MOS11 50 ; mos reverse error
LVSPLOT MOS TYPE 12 OUTPUT MOS12 50 ; dev substrate mismatch
LVSPLOT NODE TYPE 13 OUTPUT NOD13 50 ; dev pwr mismatch
;
*END
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