#The question is can PRU0 read FIFO0 while PRU1 #might try to read FIFO1 at the 
same time?
If these FIFOS are in  Data RAM it's recommended to use shared memory. What's 
confusing is as I understood it there's a PRU shared RAM and another larger 
shared memory so sample code must be inspected carefully if that's true to 
understand exactly what's being referred to as Shared. I think the larger RAM 
is called OCM.
Below and following link  is the relavent blurb to support my comment I found 
here

https://elinux.org/Ti_AM33XX_PRUSSv2

   
      - One PRU may access the memory of another for passing information but it 
is recommend to use scratch pad or shared memory, see below.
   
   - Open Core Protocol (OCP) master port
      - Access to the data bus that interconnects all peripherals on the SoC, 
including the ARM Cortex-A8, used for data transfer directly to and from the 
PRU in Level 3 (L3) memory space.

Shared Between PRUs
   
   - Scratch pad
      - 3 banks of 30 32-bit registers (total 90 32-bit registers).
      - Single-cycle access, can be accessed from either PRU for data sharing 
and signalling or for individual use.
   
   - 12KB data memory
      - Accessed over the 32-but bus, not single-cycle.
Sent from Yahoo Mail on Android 
 
  On Sun, Jun 13, 2021 at 10:38 AM, TJF<jeli.freih...@gmail.com> wrote:   
wal...@edenconceptsllc.com schrieb am Freitag, 11. Juni 2021 um 18:44:27 UTC+2:

... setting up steps 1, 2 and 3 to read three analog lines in one-shot mode 
while steps 4 & are set up to read the other two analog lines in continous 
mode.  I'll write data from steps 1, 2 and 3 into FIFO0 and 4 & 5 into FIFO1.

Yes. You can use the FIFO_select bit (26) in the STEPCONFIGx registers to 
spread the samples. And when the Mode bits (1-0) are cleared (one-shot) the 
sequencer will disable that step after operation (in STEPENABLE register). Next 
turn  the sequencer will again consider only enabled steps.


The question is can PRU0 read FIFO0 while PRU1 might try to read FIFO1 at the 
same time?

Not at the same time, but one after the other (L3 access control). AFAIR PRU-1 
waits until PRU-0 is done. And both PRUSS are waiting until ARM is done.



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