I believe it is enabled. From my last post:  the PWMSS clock config returns
CLKCONFIG 0x111 = 000100010001

According to pg 1492 of the reference manual, PWMSS_EQEP_EN is bit 4 in 
this register which appears to be true. Furthermore the interrupt timer 
register QUTMR 
is incrementing away just fine. Good idea, but no dice.

For good measure I will write this bit anyway, but with |= instead of = 
since some bits are not writable and I wouldn't want to erase the enable 
bits for pwm and ecap.


On Friday, May 9, 2014 11:33:23 PM UTC-7, James Zapico wrote:
>
> Strawson,
>
> It looks like you're not turning the PWM EQEP clock on. There should be 
> something to accomplish what this line from the kernel driver does:
>
>   // Enable the clock to the eQEP unit
>   status = pwmss_submodule_state_change(pdev->dev.parent, PWMSS_EQEPCLK_EN
> );
>
> I haven't tried this out, but it should be something like
>  *(unsigned long*)(pwm_map_base[0]+PWMSS_CLKCONFIG) = PWMSS_EQEPCLK_EN;
>
> -
> James
>
> On Friday, May 9, 2014 9:25:33 PM UTC-5, Strawson wrote:
>>
>> it seems my excitement was short-lived. While reading the position with 
>> the previous (and attached) code does work, it only does so when Teknoman's 
>> eqep driver is loaded. I've added writes to set up the PWMSS and eQEP 
>> configuration registers and have confirmed by reading them back that they 
>> are set up the same as the driver does. Any ideas on what I'm missing?
>>
>> // Write the decoder control settings
>> *(unsigned short*)(pwm_map_base[0]+EQEP_OFFSET+QDECCTL) = 0;
>> // set maximum position to two's compliment of -1, aka UINT_MAX
>> *(unsigned long*)(pwm_map_base[0]+EQEP_OFFSET+QPOSMAX)=-1;
>> // Enable interrupt
>> *(uint16_t*)(pwm_map_base[0]+EQEP_OFFSET+QEINT) = UTOF;
>> // set unit period register
>> *(unsigned long*)(pwm_map_base[0]+EQEP_OFFSET+QUPRD)=0x5F5E100;
>> // enable counter in control register
>> *(unsigned short*)(pwm_map_base[0]+EQEP_OFFSET+QEPCTL) = 
>> PHEN|IEL0|SWI|UTE|QCLM;
>>
>> SYSCONFIG 0xC
>> CLKCONFIG 0x111
>> QEPCTL0   0x9E
>> QDECCTL0  0x0
>> QEINT0    0x800
>> QUPRD0    0x5F5E100
>> QPOSMAX0  0xFFFFFFFF
>> QEPSTS0   0xA0
>> eqep0: -174 eqep1: 544 e^Cp2: 0
>>
>>
>>

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