> Hi > On Wed, 16 Nov 2005 13:00:03 +0530, varsha <[EMAIL PROTECTED]> > wrote: > > > Hello all, > > i'm using avr-gcc (GCC) 3.4.3 compiler and Atmega 16 as a MCU. > > > > for crc calculation i'm using inline assembly code. > > for example.. > > > > __asm__ __volatile__ > > ( > > "lsl r11" "\n\t" > > "rol r12" "\n\t" > > "rol r13" "\n\t" > > "rol r15" > > ); > > > > but compiler doesn't generate lsl instruction... > > it generates something like this.. > > > > 1514: bb 0c add r11, r11 > > 1516: cc 1c adc r12, r12 > > 1518: dd 1c adc r13, r13 > > 151a: ff 1c adc r15, r15 > > > > > > so what should do to if i want compiler to generate lsl instruction. > > If the bytes & execution time is the same, why should make any difference, > as long as it acheives the same result. Left shift is the same as > multiplying by 2, which is the same as adding a value to itself. Hence the > resulting code. > > --Royce. >
If you've got the code space, crc checks are far more efficiently done using a table rather than bit for bit. For an 8-bit crc, this takes 256 bytes and gives you a one-line C function for the check code. For 16-bit crc, it takes 512 bytes and two lines of C. For fast and compact assembly, you can also use a 4-bit lookup table. mvh., David _______________________________________________ AVR-GCC-list mailing list [email protected] http://lists.nongnu.org/mailman/listinfo/avr-gcc-list
