> Date: Thu, 30 Jan 2025 11:36:38 +0100 > From: Patrick Wildt <patr...@blueri.se>
Hi Patrick, After staring at the ARM ARM for a bit, I don't think the agtimer(4) bits are entirely correct. See below. The xhci(4) bits look good (but I know you're working on a better diff). So the SErrors happen because the hardware does not support 8-bit and 16-bit access to the XHCI registers. I don't think the Intel XHCI standard allows such behaviour and technically I think that means the PNP0D10 _HID should not be used. However this is easy to workaround and using a different _HID would mean OSes would need to be modified to support the USB controllers. > On Thu, Jan 30, 2025 at 07:55:11AM +0900, FUKAUMI Naoki wrote: > > Hi Patrick, > > > > On 1/30/25 00:55, Patrick Wildt wrote: > > > With some input from Jared McNeill I got OpenBSD to install and run on > > > the board, it looks like: > > > > > > * Using xhci(4) produces the SError. Jared thinks it might be missing > > > clock setup in UEFI. Disabling it allows it to run userland. > > > > It seems I used a bad install76.img. ;) > > I downloaded it again and it worked with xhci disabled. > > > > > * MP hangs. I think the cores might actually be spooled up, but as > > > soon as we try to actually run userland, there's no forward progress. > > > * SPCR enablement gets lost anytime I pull the power plug... > > > > Are you using CR1220 battery? > > I just ordered one ;) > > While I was sleeping Jared made some more progress with NetBSD, see: > > * https://mail-index.netbsd.org/source-changes/2025/01/30/msg155355.html > * https://mail-index.netbsd.org/source-changes/2025/01/30/msg155358.html > * https://mail-index.netbsd.org/source-changes/2025/01/30/msg155359.html > > With similar changes applied, OpenBSD boots up MP as well with xHCI: > > diff --git a/sys/arch/arm64/arm64/locore.S b/sys/arch/arm64/arm64/locore.S > index 54cd5922c85..62de3ef97d6 100644 > --- a/sys/arch/arm64/arm64/locore.S > +++ b/sys/arch/arm64/arm64/locore.S > @@ -81,7 +81,7 @@ drop_to_el1: > > /* Enable access to the physical timers at EL1 */ > mrs x2, cnthctl_el2 > - orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) > + mov x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) > msr cnthctl_el2, x2 I think this is right. All the unused bits in this register are RES0, so setting those to zero should be fine. And this makes sure we don't accidentally enable features that could trap into EL2. This will disable the physical timer event stream if it happens to be turn on at boot. But I don't think it should be. Linux does something very similar. > /* Set the counter offset to a known value */ > diff --git a/sys/arch/arm64/dev/agtimer.c b/sys/arch/arm64/dev/agtimer.c > index fa4e175d8ba..fe734197d4d 100644 > --- a/sys/arch/arm64/dev/agtimer.c > +++ b/sys/arch/arm64/dev/agtimer.c > @@ -324,7 +324,6 @@ void > agtimer_startclock(void) > { > struct agtimer_softc *sc = agtimer_cd.cd_devs[0]; > - uint64_t kctl; > uint32_t reg; > > if (!CPU_IS_PRIMARY(curcpu())) > @@ -341,8 +340,7 @@ agtimer_startclock(void) > clockintr_trigger(); > > /* enable userland access to virtual counter */ > - kctl = READ_SPECIALREG(CNTKCTL_EL1); > - WRITE_SPECIALREG(CNTKCTL_EL1, kctl | CNTKCTL_EL0VCTEN); > + WRITE_SPECIALREG(CNTKCTL_EL1, CNTKCTL_EL0VTEN | CNTKCTL_EL0VCTEN); > } I don't think we want to enable access to the virtual timer from userland which is what adding CNTKCTL_EL0VTEN does. So I think this should be + WRITE_SPECIALREG(CNTKCTL_EL1, CNTKCTL_EL0VCTEN); > void > diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h > index 12322dea4d6..5560ac05636 100644 > --- a/sys/arch/arm64/include/armreg.h > +++ b/sys/arch/arm64/include/armreg.h > @@ -82,6 +82,7 @@ > #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter > access*/ > > /* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ > +#define CNTKCTL_EL0VTEN (1 << 8) /* Allow EL0 virtual counter > access */ The description is wrong since this allows access to the virtual *timer*. But since I don't think we should enable this, you can drop this and leave armreg.h alone. > #define CNTKCTL_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter > access */ > > /* CNTV_CTL_EL0 */ > diff --git a/sys/dev/usb/xhcivar.h b/sys/dev/usb/xhcivar.h > index 884cd5b732e..9d5efe2a57e 100644 > --- a/sys/dev/usb/xhcivar.h > +++ b/sys/dev/usb/xhcivar.h > @@ -133,8 +133,24 @@ int xhci_intr(void *); > int xhci_detach(struct device *, int); > int xhci_activate(struct device *, int); > > -#define XREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (a)) > -#define XREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (a)) > +static inline uint8_t > +xhci_read_1(bus_space_tag_t iot, bus_space_handle_t ioh, bus_size_t offset) > +{ > + uint32_t reg; > + reg = bus_space_read_4(iot, ioh, offset & ~3); > + return (reg >> ((offset & 3) * 8)) & 0xff; > +} > + > +static inline uint16_t > +xhci_read_2(bus_space_tag_t iot, bus_space_handle_t ioh, bus_size_t offset) > +{ > + uint32_t reg; > + reg = bus_space_read_4(iot, ioh, offset & ~2); > + return (reg >> ((offset & 2) * 8)) & 0xffff; > +} > + > +#define XREAD1(sc, a) xhci_read_1((sc)->iot, (sc)->ioh, (a)) > +#define XREAD2(sc, a) xhci_read_2((sc)->iot, (sc)->ioh, (a)) > #define XREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (a)) > #define XWRITE1(sc, a, x) bus_space_write_1((sc)->iot, (sc)->ioh, (a), > (x)) > #define XWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (a), > (x)) > > > OpenBSD 7.6-current (GENERIC.MP) #608: Thu Jan 30 11:28:51 CET 2025 > patrick@windev:/usr/src/sys/arch/arm64/compile/GENERIC.MP > real mem = 16952713216 (16167MB) > avail mem = 16293490688 (15538MB) > random: good seed from bootblocks > mainbus0 at root: ACPI > psci0 at mainbus0: PSCI 1.1, SMCCC 1.2, SYSTEM_SUSPEND > efi0 at mainbus0: UEFI 2.7 > efi0: EDK II rev 0x10000 > smbios0 at efi0: SMBIOS 3.0.0 > smbios0: vendor Radxa Computer (Shenzhen) Co., Ltd. version "1.0" date Jan 1 > 1980 > smbios0: Radxa Computer (Shenzhen) Co., Ltd. Radxa Orion O6 > cpu0 at mainbus0 mpidr a00: ARM Cortex-A720 r0p1 > cpu0: 64KB 64b/line 4-way L1 PIPT I-cache, 64KB 64b/line 4-way L1 D-cache > cpu0: 512KB 64b/line 8-way L2 cache > cpu0: 12288KB 64b/line 12-way L3 cache > cpu0: > TLBIOS+IRANGE,TS+AXFLAG,FHM,DP,SM4,SM3,SHA3,RDM,Atomic,CRC32,SHA2+SHA512,SHA1,AES+PMULL,XS,I8MM,DGH,BF16,SPECRES,SB,FRINTTS,LRCPC+LDAPUR,FCMA,JSCVT,DPB+DCCVADP,GPA3,APA3+EPAC2+FPAC+COMBINED,WFXT,ECV+CNTHCTL,ASID16,AFP,PAN+ATS1E1+EPAN,LO,HPDS,VH,HAFDBS,ECBHB,IDS,AT,CSV3,CSV2+SCXT,DIT,AdvSIMD+HP,FP+HP,BT,SSBS+MSR,MTE > cpu1 at mainbus0 mpidr 0: ARM Cortex-A520 r0p1 > cpu1: 32KB 64b/line 4-way L1 PIPT I-cache, 32KB 64b/line 4-way L1 D-cache > cpu1: 12288KB 64b/line 12-way L2 cache > cpu1: mismatched ID_AA64MMFR1_EL1 > cpu1: > TLBIOS+IRANGE,TS+AXFLAG,FHM,DP,SM4,SM3,SHA3,RDM,Atomic,CRC32,SHA2+SHA512,SHA1,AES+PMULL,XS,I8MM,DGH,BF16,SPECRES,SB,FRINTTS,LRCPC+LDAPUR,FCMA,JSCVT,DPB+DCCVADP,GPA3,APA3+EPAC2+FPAC+COMBINED,WFXT,ECV+CNTHCTL,ASID16,AFP,SpecSEI,PAN+ATS1E1+EPAN,LO,HPDS,VH,HAFDBS,ECBHB,IDS,AT,CSV3,CSV2+SCXT,DIT,AdvSIMD+HP,FP+HP,BT,SSBS+MSR,MTE > cpu2 at mainbus0 mpidr 100: ARM Cortex-A520 r0p1 > cpu2: 32KB 64b/line 4-way L1 PIPT I-cache, 32KB 64b/line 4-way L1 D-cache > cpu2: 12288KB 64b/line 12-way L2 cache > cpu3 at mainbus0 mpidr 200: ARM Cortex-A520 r0p1 > cpu3: 32KB 64b/line 4-way L1 PIPT I-cache, 32KB 64b/line 4-way L1 D-cache > cpu3: 12288KB 64b/line 12-way L2 cache > cpu4 at mainbus0 mpidr 300: ARM Cortex-A520 r0p1 > cpu4: 32KB 64b/line 4-way L1 PIPT I-cache, 32KB 64b/line 4-way L1 D-cache > cpu4: 12288KB 64b/line 12-way L2 cache > cpu5 at mainbus0 mpidr 400: ARM Cortex-A720 r0p1 > cpu5: 64KB 64b/line 4-way L1 PIPT I-cache, 64KB 64b/line 4-way L1 D-cache > cpu5: 512KB 64b/line 8-way L2 cache > cpu5: 12288KB 64b/line 12-way L3 cache > cpu5: > TLBIOS+IRANGE,TS+AXFLAG,FHM,DP,SM4,SM3,SHA3,RDM,Atomic,CRC32,SHA2+SHA512,SHA1,AES+PMULL,XS,I8MM,DGH,BF16,SPECRES,SB,FRINTTS,LRCPC+LDAPUR,FCMA,JSCVT,DPB+DCCVADP,GPA3,APA3+EPAC2+FPAC+COMBINED,WFXT,ECV+CNTHCTL,ASID16,AFP,PAN+ATS1E1+EPAN,LO,HPDS,VH,HAFDBS,ECBHB,IDS,AT,CSV3,CSV2+SCXT,DIT,AdvSIMD+HP,FP+HP,BT,SSBS+MSR,MTE > cpu6 at mainbus0 mpidr 500: ARM Cortex-A720 r0p1 > cpu6: 64KB 64b/line 4-way L1 PIPT I-cache, 64KB 64b/line 4-way L1 D-cache > cpu6: 512KB 64b/line 8-way L2 cache > cpu6: 12288KB 64b/line 12-way L3 cache > cpu7 at mainbus0 mpidr 600: ARM Cortex-A720 r0p1 > cpu7: 64KB 64b/line 4-way L1 PIPT I-cache, 64KB 64b/line 4-way L1 D-cache > cpu7: 512KB 64b/line 8-way L2 cache > cpu7: 12288KB 64b/line 12-way L3 cache > cpu8 at mainbus0 mpidr 700: ARM Cortex-A720 r0p1 > cpu8: 64KB 64b/line 4-way L1 PIPT I-cache, 64KB 64b/line 4-way L1 D-cache > cpu8: 512KB 64b/line 8-way L2 cache > cpu8: 12288KB 64b/line 12-way L3 cache > cpu9 at mainbus0 mpidr 800: ARM Cortex-A720 r0p1 > cpu9: 64KB 64b/line 4-way L1 PIPT I-cache, 64KB 64b/line 4-way L1 D-cache > cpu9: 512KB 64b/line 8-way L2 cache > cpu9: 12288KB 64b/line 12-way L3 cache > cpu10 at mainbus0 mpidr 900: ARM Cortex-A720 r0p1 > cpu10: 64KB 64b/line 4-way L1 PIPT I-cache, 64KB 64b/line 4-way L1 D-cache > cpu10: 512KB 64b/line 8-way L2 cache > cpu10: 12288KB 64b/line 12-way L3 cache > cpu11 at mainbus0 mpidr b00: ARM Cortex-A720 r0p1 > cpu11: 64KB 64b/line 4-way L1 PIPT I-cache, 64KB 64b/line 4-way L1 D-cache > cpu11: 512KB 64b/line 8-way L2 cache > cpu11: 12288KB 64b/line 12-way L3 cache > apm0 at mainbus0 > agintc0 at mainbus0 shift 4:4 nirq 544 nredist 12 ipi: 0, 1, 2: > "interrupt-controller" > agintcmsi0 at agintc0 > agtimer0 at mainbus0: 1000000 kHz > acpi0 at mainbus0: ACPI 5.1 > acpi0: sleep states > acpi0: tables DSDT FACP SSDT CSRT DBG2 GTDT IORT SDEI SPCR APIC SSDT MCFG > acpi0: wakeup devices > acpiiort0 at acpi0 > acpimcfg0 at acpi0 > acpimcfg0: addr 0x20000000, bus 144-175 > acpimcfg0: addr 0x20000000, bus 48-79 > acpimcfg0: addr 0x20000000, bus 0-31 > "CIXHA016" at acpi0 not configured > "CIXHA017" at acpi0 not configured > "CIXHA018" at acpi0 not configured > pluart0 at acpi0 COM0 addr 0x40b0000/0x10000 irq 328 > pluart1 at acpi0 COM1 addr 0x40c0000/0x10000 irq 329 > pluart2 at acpi0 COM2 addr 0x40d0000/0x10000 irq 330 > pluart2: console > "PRP0001" at acpi0 not configured > "PRP0001" at acpi0 not configured > "PRP0001" at acpi0 not configured > "CIXHA019" at acpi0 not configured > "CIXHA001" at acpi0 not configured > "CIXHA001" at acpi0 not configured > "CIXHA001" at acpi0 not configured > "CIXHA001" at acpi0 not configured > "CIXHA010" at acpi0 not configured > "CIXA1019" at acpi0 not configured > "CIXHA020" at acpi0 not configured > "CIXHA021" at acpi0 not configured > "CIXHA018" at acpi0 not configured > "CIXHA018" at acpi0 not configured > "CIXH7020" at acpi0 not configured > "CIXHA004" at acpi0 not configured > "CIXHA005" at acpi0 not configured > "CIXHA006" at acpi0 not configured > "CIXHA008" at acpi0 not configured > "CIXHA009" at acpi0 not configured > "CIXHA000" at acpi0 not configured > "CIXHA007" at acpi0 not configured > "CIXH6060" at acpi0 not configured > "CIXH6061" at acpi0 not configured > "CIXH6062" at acpi0 not configured > "CIXHA018" at acpi0 not configured > "CIXH1002" at acpi0 not configured > "CIXH1003" at acpi0 not configured > "CIXH1003" at acpi0 not configured > "CIXH1003" at acpi0 not configured > "CIXH1003" at acpi0 not configured > "CIXH1003" at acpi0 not configured > "CIXH2011" at acpi0 not configured > "CIXH1007" at acpi0 not configured > "CIXH6020" at acpi0 not configured > "CIXHA018" at acpi0 not configured > "CIXH6000" at acpi0 not configured > "CIXHA014" at acpi0 not configured > "CIXH1006" at acpi0 not configured > "CIXH302C" at acpi0 not configured > "CIXH3024" at acpi0 not configured > "CIXH3023" at acpi0 not configured > "CIXH200B" at acpi0 not configured > "CIXH200D" at acpi0 not configured > "CIXH200D" at acpi0 not configured > "RTL5682" at acpi0 not configured > "CIXHA011" at acpi0 not configured > "CIXH200B" at acpi0 not configured > "RX8900" at acpi0 not configured > "CIXH3024" at acpi0 not configured > "CIXH200B" at acpi0 not configured > "CIXH3024" at acpi0 not configured > "CIXH200B" at acpi0 not configured > "CIXH200B" at acpi0 not configured > "CIXH200D" at acpi0 not configured > "CIXH200D" at acpi0 not configured > "CIXH2001" at acpi0 not configured > "SPT0001" at acpi0 not configured > "CIXH2001" at acpi0 not configured > "SPT0002" at acpi0 not configured > acpipci0 at acpi0 PCI1 > pci0 at acpipci0 > ppb0 at pci0 dev 0 function 0 vendor "Cadence", unknown product 0x0100 rev > 0x00 > pci1 at ppb0 bus 145 > nvme0 at pci1 dev 0 function 0 "Samsung PM9A1 NVMe" rev 0x00: msix, NVMe 1.4 > nvme0: XXXXXXXXXXXX-XXXXX, firmware XXXXXXXX, serial XXXXXXXXXXXXXX > scsibus0 at nvme0: 2 targets, initiator 0 > sd0 at scsibus0 targ 1 lun 0: <NVMe, XXXXXXXXXXXX-XXX, XXXX> > sd0: 488386MB, 512 bytes/sector, 1000215216 sectors > acpipci1 at acpi0 PCI3 > pci2 at acpipci1 > ppb1 at pci2 dev 0 function 0 vendor "Cadence", unknown product 0x0100 rev > 0x00 > pci3 at ppb1 bus 49 > rge0 at pci3 dev 0 function 0 "Realtek RTL8126" rev 0x01: msix, address > XX:XX:XX:XX:XX:XX > acpipci2 at acpi0 PCI4 > pci4 at acpipci2 > ppb2 at pci4 dev 0 function 0 vendor "Cadence", unknown product 0x0100 rev > 0x00 > pci5 at ppb2 bus 1 > 1:0:0: io address conflict 0x1000/0x100 > rge1 at pci5 dev 0 function 0 "Realtek RTL8126" rev 0x01: msix, address > XX:XX:XX:XX:XX:XX > "CIXH2020" at acpi0 not configured > "CIXH2023" at acpi0 not configured > "CIXH2020" at acpi0 not configured > "CIXH2020" at acpi0 not configured > "CIXH2023" at acpi0 not configured > "CIXH3010" at acpi0 not configured > "CIXH502F" at acpi0 not configured > "CIXH502F" at acpi0 not configured > "CIXH502F" at acpi0 not configured > "CIXH502F" at acpi0 not configured > "CIXH502F" at acpi0 not configured > "CIXH5010" at acpi0 not configured > "CIXH5010" at acpi0 not configured > "CIXH5010" at acpi0 not configured > "CIXH5010" at acpi0 not configured > "CIXH5010" at acpi0 not configured > "CIXH5041" at acpi0 not configured > "CIXH5040" at acpi0 not configured > "CIXHA012" at acpi0 not configured > "CIXHA013" at acpi0 not configured > "CIXH5000" at acpi0 not configured > "CIXH4000" at acpi0 not configured > xhci0 at acpi0 XHC0 addr 0x9018000/0x8000 irq 294, xHCI 1.10 > usb0 at xhci0: USB revision 3.0 > uhub0 at usb0 configuration 1 interface 0 "Generic xHCI root hub" rev > 3.00/1.00 addr 1 > xhci1 at acpi0 XHC2 addr 0x90f8000/0x8000 irq 306, xHCI 1.10 > usb1 at xhci1: USB revision 3.0 > uhub1 at usb1 configuration 1 interface 0 "Generic xHCI root hub" rev > 3.00/1.00 addr 1 > xhci2 at acpi0 XHC4 addr 0x91d8000/0x8000 irq 284, xHCI 1.10 > usb2 at xhci2: USB revision 3.0 > uhub2 at usb2 configuration 1 interface 0 "Generic xHCI root hub" rev > 3.00/1.00 addr 1 > xhci3 at acpi0 XHC5 addr 0x91e8000/0x8000 irq 289, xHCI 1.10 > usb3 at xhci3: USB revision 3.0 > uhub3 at usb3 configuration 1 interface 0 "Generic xHCI root hub" rev > 3.00/1.00 addr 1 > xhci4 at acpi0 USB0 addr 0x9268000/0x8000 irq 272, xHCI 1.10 > usb4 at xhci4: USB revision 3.0 > uhub4 at usb4 configuration 1 interface 0 "Generic xHCI root hub" rev > 3.00/1.00 addr 1 > xhci5 at acpi0 USB1 addr 0x9298000/0x8000 irq 275, xHCI 1.10 > usb5 at xhci5: USB revision 3.0 > uhub5 at usb5 configuration 1 interface 0 "Generic xHCI root hub" rev > 3.00/1.00 addr 1 > xhci6 at acpi0 USB2 addr 0x92c8000/0x8000 irq 278, xHCI 1.10 > usb6 at xhci6: USB revision 3.0 > uhub6 at usb6 configuration 1 interface 0 "Generic xHCI root hub" rev > 3.00/1.00 addr 1 > xhci7 at acpi0 USB3 addr 0x92f8000/0x8000 irq 281, xHCI 1.10 > usb7 at xhci7: USB revision 3.0 > uhub7 at usb7 configuration 1 interface 0 "Generic xHCI root hub" rev > 3.00/1.00 addr 1 > "CIXH2030" at acpi0 not configured > "CIXH2031" at acpi0 not configured > "CIXH2032" at acpi0 not configured > "CIXH2033" at acpi0 not configured > "CIXH2031" at acpi0 not configured > "CIXH2032" at acpi0 not configured > "CIXH2033" at acpi0 not configured > "CIXH2030" at acpi0 not configured > "CIXH2031" at acpi0 not configured > "CIXH2032" at acpi0 not configured > "CIXH2033" at acpi0 not configured > "CIXH2031" at acpi0 not configured > "CIXH2032" at acpi0 not configured > "CIXH2033" at acpi0 not configured > "CIXH2030" at acpi0 not configured > "CIXH2031" at acpi0 not configured > "CIXH2030" at acpi0 not configured > "CIXH2031" at acpi0 not configured > "CIXH2032" at acpi0 not configured > "CIXH2032" at acpi0 not configured > "CIXH2034" at acpi0 not configured > "CIXH2030" at acpi0 not configured > "CIXH2031" at acpi0 not configured > "CIXH2030" at acpi0 not configured > "CIXH2031" at acpi0 not configured > "CIXH2032" at acpi0 not configured > "CIXH2032" at acpi0 not configured > "CIXH2030" at acpi0 not configured > "CIXH2031" at acpi0 not configured > "CIXH2032" at acpi0 not configured > "CIXH2030" at acpi0 not configured > "CIXH2031" at acpi0 not configured > "CIXH2032" at acpi0 not configured > "CIXH3020" at acpi0 not configured > "CIXH3021" at acpi0 not configured > "CIXH3025" at acpi0 not configured > "CIXH3026" at acpi0 not configured > "CIXH3027" at acpi0 not configured > "CIXH3028" at acpi0 not configured > "CIXH3029" at acpi0 not configured > "CIXH302A" at acpi0 not configured > "CIXH302B" at acpi0 not configured > "CIXHA022" at acpi0 not configured > "CIXH6030" at acpi0 not configured > "CIXH6070" at acpi0 not configured > "CIXHA015" at acpi0 not configured > acpibat0 at acpi0: BAT0 not present > "PNP0C0B" at acpi0 not configured > acpibtn0 at acpi0: PWRB > acpibtn1 at acpi0: LID_ > acpiac0 at acpi0: AC unit offline > "PNP0C50" at acpi0 not configured > "PNP0C14" at acpi0 not configured > acpitz0 at acpi0: no critical temperature defined > acpipwrres0 at acpi0: PPRS, resource for ACLK > acpipwrres1 at acpi0: PPRS, resource for VPU0 > acpipwrres2 at acpi0: PRS0, resource for CRE0 > acpipwrres3 at acpi0: PRS1, resource for CRE1 > acpipwrres4 at acpi0: PRS2, resource for CRE2 > acpipwrres5 at acpi0: PRS3, resource for CRE3 > acpipwrres6 at acpi0: PRS0, resource for DPU0 > acpipwrres7 at acpi0: PRS1, resource for DPU1 > acpipwrres8 at acpi0: PRS2, resource for DPU2 > acpipwrres9 at acpi0: PRS3, resource for DPU3 > acpipwrres10 at acpi0: PRS4, resource for DPU4 > acpipwrres11 at acpi0: PPRS, resource for GPU_ > acpipwrres12 at acpi0: PPRS, resource for NPU0, CRE0, CRE1, CRE2 > acpipwrres13 at acpi0: PRS0, resource for CRE0 > acpipwrres14 at acpi0: PRS1, resource for CRE1 > acpipwrres15 at acpi0: PRS2, resource for CRE2 > acpipwrres16 at acpi0: PRS0, resource for ISPM > acpipwrres17 at acpi0: ECFN, resource for ECFP > acpitz1 at acpi0acpitz1: ECTZ: failed to read _TMP > acpitz1: ECTZ: failed to read _TMP > > vscsi0 at root > scsibus1 at vscsi0: 256 targets > softraid0 at root > scsibus2 at softraid0: 256 targets > root on sd0a (8bab913958cbd5cf.a) swap on sd0b dump on sd0b > WARNING: CHECK AND RESET THE DATE! > Automatic boot in progress: starting file system checks. > /dev/sd0a (8bab913958cbd5cf.a): file system is clean; not checking > /dev/sd0j (8bab913958cbd5cf.j): file system is clean; not checking > /dev/sd0d (8bab913958cbd5cf.d): file system is clean; not checking > /dev/sd0f (8bab913958cbd5cf.f): file system is clean; not checking > /dev/sd0g (8bab913958cbd5cf.g): file system is clean; not checking > /dev/sd0h (8bab913958cbd5cf.h): file system is clean; not checking > /dev/sd0e (8bab913958cbd5cf.e): file system is clean; not checking > pf enabled > kern.allowkmem: 0 -> 1 > starting network > reordering: ld.so libc libcrypto sshd sshd-session sshd-auth ssh-agent. > starting early daemons: syslogd pflogd ntpd. > starting RPC daemons:. > savecore: no core dump > checking quotas: done. > clearing /tmp > kern.securelevel: 0 -> 1 > creating runtime link editor directory cache. > preserving editor files. > starting network daemons: sshd smtpd sndiod. > starting local daemons: cron. > Thu Jan 30 11:29:35 CET 2025 > > OpenBSD/arm64 (orion) (console) > > login: >
