On Wed, Dec 08, 2021 at 05:20:39PM +0100, Mark Kettenis wrote:
Date: Wed, 8 Dec 2021 16:31:50 +0100
From: Christopher Zimmermann <chr...@openbsd.org>
>On Wed, Dec 08, 2021 at 10:47:45AM +0100, Christopher Zimmermann wrote:
>> Note that it attaches to "snps,dw-wdt"
On Wed, Dec 08, 2021 at 08:57:53PM +1100, Jonathan Gray wrote:
>We already have a driver for that.
Oh no.
OK?
What problem are you trying to solve?
I want a watchdog.
This morning I sent a full featured watchdog driver to the list not
knowing there already was a driver for rebooting. I would like to merge
those drivers.
Here's an attempt at merging your reset-only driver with my watchdog
driver. Not yet tested. I need to go to work now...
/* $OpenBSD: dwdog.c,v 1.3 2020/05/29 04:42:25 deraadt Exp $
*/
/*
* Copyright (c) 2017 Mark Kettenis <kette...@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <machine/intr.h>
#include <machine/bus.h>
#include <machine/fdt.h>
#include <armv7/armv7/armv7_machdep.h>
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_clock.h>
#include <dev/ofw/fdt.h>
/* Registers */
#define DWDOG_CR 0x0000 /* control */
#define DWDOG_CR_ENABLE 0x0001 /* enable counter */
#define DWDOG_CR_INTERRUPT 0x0002
/*
* On some devices DWDOG_CR_ENABLE can only be set, but not be cleared.
*
* If DWDOG_CR_INTERRUPT is enabled the watchdog will count twice. After the
* first count the interrupt is raised as a warning. After the second count
* reset happens only when the interrupt is not cleared.
*/
#define DWDOG_CR_RST_PULSE_LENGTH_MASK 0x001c
#define DWDOG_CR_RST_PULSE_LENGTH_SHIFT 2
/*
* 000: 2 pclk cycles
* 001: 4 pclk cycles
* 010: 8 pclk cycles DEFAULT
* 011: 16 pclk cycles
* 100: 32 pclk cycles
* 101: 64 pclk cycles
* 110: 128 pclk cycles
* 111: 256 pclk cycles
*/
/* timeout range n={0..15}. Timeout is 2^(16+n)-1 ticks */
#define DWDOG_TORR 0x0004
#define DWDOG_CCVR 0x0008 /* current counter value */
#define DWDOG_CRR 0x000c /* counter restart by writing code
number */
#define DWDOG_CRR_MAGIC 0x76
#define DWDOG_STAT 0x0010 /* interrupt status */
#define DWDOG_EOI 0x0014 /* clear interrupt */
#define HREAD4(sc, reg) \
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
#define HWRITE4(sc, reg, val) \
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
struct dwdog_softc {
struct device sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
uint32_t sc_freq;
int sc_period;
int sc_reset;
};
int dwdog_match(struct device *, void *, void *);
void dwdog_attach(struct device *, struct device *, void *);
static void dwdog_dump(struct dwdog_softc *, const char *);
int dwdog_intr(void *);
int dwdog_cb(void *, int);
void dwdog_reset(void);
struct cfattach dwdog_ca = {
sizeof (struct dwdog_softc), dwdog_match, dwdog_attach
};
struct cfdriver dwdog_cd = {
NULL, "dwdog", DV_DULL
};
int
dwdog_match(struct device *parent, void *match, void *aux)
{
struct fdt_attach_args *faa = aux;
return OF_is_compatible(faa->fa_node, "snps,dw-wdt");
}
void
dwdog_attach(struct device *parent, struct device *self, void *aux)
{
struct dwdog_softc *sc = (struct dwdog_softc *)self;
struct fdt_attach_args *faa = aux;
if (faa->fa_nreg < 1) {
printf(": no registers\n");
return;
}
sc->sc_iot = faa->fa_iot;
if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
faa->fa_reg[0].size, 0, &sc->sc_ioh)) {
printf(": can't map registers\n");
return;
}
if (HREAD4(sc, DWDOG_CR) != 0x0a) {
printf(" unexpected (expected 0xa)\n");
return;
}
fdt_intr_establish(faa->fa_node, IPL_CLOCK, dwdog_intr,
sc, sc->sc_dev.dv_xname);
if (NULL == fdt_intr_establish(faa->fa_node, IPL_BIO,
dwdog_intr, sc, sc->sc_dev.dv_xname)) {
printf(": unable to establish interrupt\n");
return;
}
printf("\n");
sc->sc_freq = 0;
dwdog_dump(sc, "initial dump");
#ifndef SMALL_KERNEL
wdog_register(dwdog_cb, sc);
#endif
clock_set_assigned(faa->fa_node);
clock_enable_all(faa->fa_node);
if (cpuresetfn == NULL)
cpuresetfn = dwdog_reset;
}
static void
dwdog_dump(struct dwdog_softc *sc, const char *msg) {
#ifdef DEBUG
printf("%s: %s\n CR=%#x TORR=%#x(%u) CCVR=%#x STAT=%#x\n",
sc->sc_dev.dv_xname, msg,
HREAD4(sc, DWDOG_CR),
HREAD4(sc, DWDOG_TORR),
HREAD4(sc, DWDOG_TORR),
HREAD4(sc, DWDOG_CCVR),
HREAD4(sc, DWDOG_STAT));
#endif
}
int
dwdog_intr(void *self) {
struct dwdog_softc *sc = self;
dwdog_dump(sc, "interrupt");
/* clear all interrupts */
HREAD4(sc, DWDOG_EOI);
return 1;
}
int
dwdog_cb(void *self, int period)
{
struct dwdog_softc *sc = self;
unsigned tor = 0;
uint32_t control;
dwdog_dump(sc, "watchdog callback");
/*
* to enable set RC_ENABLE and clear RC_INTERRUPT
* to disable clear RC_ENABLE and set RC_INTERRUPT
* Even when RC_ENABLE cannot be cleared this prevents a reset because
* we acknowledge all interrupts.
*/
if (sc->sc_reset)
return -1;
if (period > 0 && period == sc->sc_period) {
#ifdef DEBUG
printf("%s: just tickling\n", sc->sc_dev.dv_xname);
#endif
HWRITE4(sc, DWDOG_CRR, DWDOG_CRR_MAGIC);
return sc->sc_period;
}
control = HREAD4(sc, DWDOG_CR);
if (period == 0) {
/* in case counter cannot be disabled enable interrupt */
if ((control & DWDOG_CR_ENABLE) == 0)
return 0;
HWRITE4(sc, DWDOG_TORR, 15);
control &= ~DWDOG_CR_ENABLE;
control |= DWDOG_CR_INTERRUPT;
HWRITE4(sc, DWDOG_CR, control);
control = HREAD4(sc, DWDOG_CR);
if (control & DWDOG_CR_ENABLE) {
/* we don't enable without measuring freq */
printf("%s: Cannot disable watchdog timer. "
"Please enable kern.watchdog.auto as a
workaround\n",
sc->sc_dev.dv_xname);
return (0x7fffffff / sc->sc_freq);
}
else
return 0;
}
if (sc->sc_freq == 0) {
uint32_t ticks, dt = 1000; /* us */
HWRITE4(sc, DWDOG_TORR, 15);
control |= DWDOG_CR_ENABLE | DWDOG_CR_INTERRUPT;
HWRITE4(sc, DWDOG_CR, control);
HWRITE4(sc, DWDOG_CRR, DWDOG_CRR_MAGIC);
ticks = HREAD4(sc, DWDOG_CCVR);
delay(dt);
ticks -= HREAD4(sc, DWDOG_CCVR);
sc->sc_freq = ticks * (1000000 / dt);
#ifdef DEBUG
printf("%s: %d / %u us => frequency %u\n",
sc->sc_dev.dv_xname, ticks, dt, sc->sc_freq);
#endif
}
while (tor < 15 &&
1 << tor < (sc->sc_freq >> 16) * period)
tor++;
#ifdef DEBUG
printf("%s: target period=%ds ticks_wanted=%u tor=%u ticks=%#x(%u /
%us)\n",
sc->sc_dev.dv_xname,
period,
sc->sc_freq * period - 1,
tor,
(1 << (16+tor)) - 1,
(1 << (16+tor)) - 1,
((1 << (16+tor)) - 1) / sc->sc_freq);
#endif
assert((1 << (16+tor)) - 1 >= sc->sc_freq);
sc->sc_period = ((1 << (16+tor)) - 1) / sc->sc_freq;
HWRITE4(sc, DWDOG_TORR, tor);
control = HREAD4(sc, DWDOG_CR);
control |= DWDOG_CR_ENABLE;
control &= ~DWDOG_CR_INTERRUPT;
HWRITE4(sc, DWDOG_CR, control);
HWRITE4(sc, DWDOG_CRR, DWDOG_CRR_MAGIC);
dwdog_dump(sc, "started watchdog");
return sc->sc_period;
}
void
dwdog_reset(void)
{
struct dwdog_softc *sc = dwdog_cd.cd_devs[0];
uint32_t control;
/*
* Generate system reset when timer expires and select
* smallest timeout.
*/
sc->sc_reset = 1;
control = HREAD4(sc, DWDOG_CR);
control &= ~DWDOG_CR_INTERRUPT;
control |= ~DWDOG_CR_ENABLE;
HWRITE4(sc, DWDOG_TORR, 0);
HWRITE4(sc, DWDOG_CR, control);
HWRITE4(sc, DWDOG_CRR, DWDOG_CRR_MAGIC);
delay(1000000);
}
