Hello,
> That's not right. The reg property needs to be translated through
> all necessary layers. This only works if the phy is in the same
> layer as the ehci. Feels like a hack.
Is there any good documentation to understand OF_xxx() api calls?
I'm new to hack this area, I wrote that patch by reading OpenBSD's
sourcecode with many trial and error.
I think your sxiuphy is very good idea, and I am trying to
test this driver.
But there is a problem that current sxiuphy cannot access
USB PHY register of Allwinner V3s even if I add clock_enable() and
reset_deassert_all() after bus_space_map().
I checked behavior of USB PHY register, and I found that this module
requires one of {EHCI, OHCI, OTG} clock and its own clock.
So, sxiuphy requires to start *after* ehci/ohci (or musb-otg) driver
when running them on Allwinner V3s. How about on other Allwinner SoC?
If it is difficult to change order to boot sxiuphy driver,
we have to consider to add some code to ehci_fdt.c or something other.
Here is the log that I tested on U-boot.
----
U-Boot 2019.01 (Feb 20 2019 - 13:01:02 +0900) Allwinner Technology
CPU: Allwinner V3s (SUN8I 1681)
Model: Lichee Pi Zero
DRAM: 64 MiB
MMC: SUNXI SD/MMC: 0
Loading Environment from FAT... *** Warning - bad CRC, using default environment
In: serial@01c28000
Out: serial@01c28000
Err: serial@01c28000
Net: No ethernet found.
starting USB...
No controllers found
Hit any key to stop autoboot: 0
=> md 01c20060 1 *BUS_CLK_GATING_REG0: OHCI/EHCI/OTG clock off
01c20060: 00004140 @A..
=> md 01c202c0 1 *BUS_SOFT_RST_REG0: OHCI/EHCI/OTG are reset
01c202c0: 00004140 @A..
=> md 01c200cc 1 *USBPHY_CFG_REG: OHCI/PHY clock off, PHY reset
01c200cc: 00000000 ....
=> md 01c19400 b *USBPHY register access failed
01c19400: 00000000 00000000 00000000 00000000 ................
01c19410: 00000000 00000000 00000000 00000000 ................
01c19420: 00000000 00000000 00000000 ............
=> mw 01c200cc 00000101 *USBPHY_CFG_REG: PHY clock on, reset deassert
=> md 01c19400 b *USBPHY register access failed
01c19400: 00000000 00000000 00000000 00000000 ................
01c19410: 00000000 00000000 00000000 00000000 ................
01c19420: 00000000 00000000 00000000 ............
=> mw 01c20060 01004140 *BUS_CLK_GATING_REG0: OTG clock on
=> md 01c19400 b *USBPHY register access success
01c19400: 40000000 00000000 00000000 00000000 ...@............
01c19410: 00000002 00000000 023438e4 00000000 .........84.....
01c19420: 00000001 00000000 00000000 ............
=> mw 01c20060 04004140 *BUS_CLK_GATING_REG0: EHCI clock on
=> md 01c19400 b *USBPHY register access success
01c19400: 40000000 00000000 00000000 00000000 ...@............
01c19410: 00000002 00000000 023438e4 00000000 .........84.....
01c19420: 00000001 00000000 00000000 ............
=> mw 01c20060 20004140 *BUS_CLK_GATING_REG0: OHCI clock on
=> md 01c19400 b *USBPHY register access success
01c19400: 40000000 00000000 00000000 00000000 ...@............
01c19410: 00000002 00000000 023438e4 00000000 .........84.....
01c19420: 00000001 00000000 00000000 ............
=> mw 01c20060 00004140 *BUS_CLK_GATING_REG0: OHCI/EHCI/OTG clock off
=> md 01c19400 b *USBPHY register access failed
01c19400: 00000000 00000000 00000000 00000000 ................
01c19410: 00000000 00000000 00000000 00000000 ................
01c19420: 00000000 00000000 00000000 ............
=>
Regards,
--
SASANO Takayoshi (JG1UAA) <u...@mx5.nisiq.net>
