[PATCH 24/28] drm/amd/display: Use optc32 instead of optc30 in DC

[Rodrigo Siqueira]

From: Ovidiu Bunea <ovidiu.bu...@amd.com>

Change DC to use optc32, which uses REG_UPDATE instead of REG_SET.
REG_SET clears OTG_H_TIMING_DIV_MODE_MANUAL which must be set to 1 for
FRL DSC.

Reviewed-by: Charlene Liu <charlene....@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bu...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | 2 ++
 drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index 5bf4d0aa6230..b97bdb868a0e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -207,7 +207,7 @@ void optc3_set_odm_bypass(struct timing_generator *optc,
                        );
 
        h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
-       REG_SET(OTG_H_TIMING_CNTL, 0,
+       REG_UPDATE(OTG_H_TIMING_CNTL,
                        OTG_H_TIMING_DIV_MODE, h_div);
 
        REG_SET(OPTC_MEMORY_CONFIG, 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
index e7e25c58c692..a2c4db2cebdd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -201,7 +201,7 @@ static void optc32_disable_phantom_otg(struct 
timing_generator *optc)
        REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
 }
 
-static void optc32_set_odm_bypass(struct timing_generator *optc,
+void optc32_set_odm_bypass(struct timing_generator *optc,
                const struct dc_crtc_timing *dc_crtc_timing)
 {
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
index 93cc7fc8472c..8ce3b178cab0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
@@ -181,5 +181,7 @@
 void dcn32_timing_generator_init(struct optc *optc1);
 void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool 
manual_mode);
 void optc32_get_odm_combine_segments(struct timing_generator *tg, int 
*odm_combine_segments);
+void optc32_set_odm_bypass(struct timing_generator *optc,
+               const struct dc_crtc_timing *dc_crtc_timing);
 
 #endif /* __DC_OPTC_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c
index 2bea1e475096..b0c068240a94 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c
@@ -249,7 +249,7 @@ static struct timing_generator_funcs dcn35_tg_funcs = {
                .set_dsc_config = optc3_set_dsc_config,
                .get_dsc_status = optc2_get_dsc_status,
                .set_dwb_source = NULL,
-               .set_odm_bypass = optc3_set_odm_bypass,
+               .set_odm_bypass = optc32_set_odm_bypass,
                .set_odm_combine = optc35_set_odm_combine,
                .get_optc_source = optc2_get_optc_source,
                .set_h_timing_div_manual_mode = 
optc32_set_h_timing_div_manual_mode,
-- 
2.40.1