[PATCH 13/22] drm/amd/display: Revert "dc: read down-spread percentage from lut to adjust dprefclk"

[Tom Chung]

From: Leo Chen <sancc...@amd.com>

[Why & How]
Revert commit feb90174e9c6 ("drm/amd/display: Read down-spread percentage from 
lut to adjust dprefclk.")
This change was causing 240hz display to not light up after s0i3.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Acked-by: Tom Chung <chiahsuan.ch...@amd.com>
Signed-off-by: Leo Chen <sancc...@amd.com>
---
 .../dc/clk_mgr/dcn314/dcn314_clk_mgr.c        | 32 +------------------
 .../dc/clk_mgr/dcn314/dcn314_clk_mgr.h        |  7 ----
 2 files changed, 1 insertion(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index 3ba2e13d691d..7326b7565846 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -87,14 +87,6 @@ static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 
0x02401800, 0, 0, 0,
 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK     0x0000F000L
 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK     0xFFFF0000L
 
-#define regCLK1_CLK2_BYPASS_CNTL                       0x029c
-#define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX      0
-
-#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT  0x0
-#define CLK1_CLK2_BYPASS_CNTL__LK2_BYPASS_DIV__SHIFT   0x10
-#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK            0x00000007L
-#define CLK1_CLK2_BYPASS_CNTL__LK2_BYPASS_DIV_MASK             0x000F0000L
-
 #define REG(reg_name) \
        (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## 
reg_name)
 
@@ -444,11 +436,6 @@ static DpmClocks314_t dummy_clocks;
 
 static struct dcn314_watermarks dummy_wms = { 0 };
 
-static struct dcn314_ss_info_table ss_info_table = {
-       .ss_divider = 1000,
-       .ss_percentage = {0, 0, 375, 375, 375}
-};
-
 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, 
struct dcn314_watermarks *table)
 {
        int i, num_valid_sets;
@@ -728,20 +715,6 @@ static struct clk_mgr_funcs dcn314_funcs = {
 };
 extern struct clk_mgr_funcs dcn3_fpga_funcs;
 
-static void dcn314_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
-{
-       uint32_t clock_source;
-
-       REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source);
-
-       clk_mgr->dprefclk_ss_percentage = 
ss_info_table.ss_percentage[clock_source];
-
-       if (clk_mgr->dprefclk_ss_percentage != 0) {
-               clk_mgr->ss_on_dprefclk = true;
-               clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
-       }
-}
-
 void dcn314_clk_mgr_construct(
                struct dc_context *ctx,
                struct clk_mgr_dcn314 *clk_mgr,
@@ -808,11 +781,8 @@ void dcn314_clk_mgr_construct(
 
        clk_mgr->base.base.dprefclk_khz = 600000;
        clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
-
-       dcn314_read_ss_info_from_lut(&clk_mgr->base);
+       dce_clock_read_ss_info(&clk_mgr->base);
        /*if bios enabled SS, driver needs to adjust dtb clock, only enable 
with correct bios*/
-       clk_mgr->base.base.dprefclk_khz =
-               dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, 
clk_mgr->base.base.dprefclk_khz);
 
        clk_mgr->base.base.bw_params = &dcn314_bw_params;
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h
index e0670dafe260..171f84340eb2 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h
@@ -28,8 +28,6 @@
 #define __DCN314_CLK_MGR_H__
 #include "clk_mgr_internal.h"
 
-#define NUM_CLOCK_SOURCES   5
-
 struct dcn314_watermarks;
 
 struct dcn314_smu_watermark_set {
@@ -42,11 +40,6 @@ struct clk_mgr_dcn314 {
        struct dcn314_smu_watermark_set smu_wm_set;
 };
 
-struct dcn314_ss_info_table {
-       uint32_t ss_divider;
-       uint32_t ss_percentage[NUM_CLOCK_SOURCES];
-};
-
 bool dcn314_are_clock_states_equal(struct dc_clocks *a,
                struct dc_clocks *b);
 
-- 
2.25.1