add session context buffer to decoder ring test for vcn v1 to v3.
Signed-off-by: Saleemkhan Jamadar <saleemkhan.jama...@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrish...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 33 ++++++++++++++++++-------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 +++-
2 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 4e1256af80b6..56fb66f1d2d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -539,6 +539,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
struct dma_fence **fence)
{
u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
+ uint64_t session_ctx_buf_gaddr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr
+ 8192);
struct amdgpu_device *adev = ring->adev;
struct dma_fence *f = NULL;
struct amdgpu_job *job;
@@ -552,13 +553,23 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring
*ring,
goto err;
ib = &job->ibs[0];
- ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
- ib->ptr[1] = addr;
- ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
- ib->ptr[3] = addr >> 32;
- ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
- ib->ptr[5] = 0;
- for (i = 6; i < 16; i += 2) {
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = PACKET0(adev->vcn.internal.data0, 0);
+ ib->ptr[ib->length_dw++] = lower_32_bits(session_ctx_buf_gaddr);
+ ib->ptr[ib->length_dw++] = PACKET0(adev->vcn.internal.data1, 0);
+ ib->ptr[ib->length_dw++] = upper_32_bits(session_ctx_buf_gaddr);
+ /* session ctx buffer cmd */
+ ib->ptr[ib->length_dw++] = PACKET0(adev->vcn.internal.cmd, 0);
+ ib->ptr[ib->length_dw++] = 0xa;
+
+ ib->ptr[ib->length_dw++] = PACKET0(adev->vcn.internal.data0, 0);
+ ib->ptr[ib->length_dw++] = lower_32_bits(addr);
+ ib->ptr[ib->length_dw++] = PACKET0(adev->vcn.internal.data1, 0);
+ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
+ ib->ptr[ib->length_dw++] = PACKET0(adev->vcn.internal.cmd, 0);
+ ib->ptr[ib->length_dw++] = 0;
+
+ for (i = ib->length_dw; i < 16; i += 2) {
ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
ib->ptr[i+1] = 0;
}
@@ -591,13 +602,15 @@ static int amdgpu_vcn_dec_get_create_msg(struct
amdgpu_ring *ring, uint32_t hand
int r, i;
memset(ib, 0, sizeof(*ib));
- r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
+ /* 34 pages : 128KiB session context buffer size and 8KiB ib msg */
+ r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 34,
AMDGPU_IB_POOL_DIRECT,
ib);
if (r)
return r;
msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
+ memset(msg, 0, (AMDGPU_GPU_PAGE_SIZE * 34));
msg[0] = cpu_to_le32(0x00000028);
msg[1] = cpu_to_le32(0x00000038);
msg[2] = cpu_to_le32(0x00000001);
@@ -626,13 +639,15 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct
amdgpu_ring *ring, uint32_t han
int r, i;
memset(ib, 0, sizeof(*ib));
- r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
+ /* 34 pages : 128KiB session context buffer size and 8KiB ib msg */
+ r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 34,
AMDGPU_IB_POOL_DIRECT,
ib);
if (r)
return r;
msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
+ memset(msg, 0, (AMDGPU_GPU_PAGE_SIZE * 34));
msg[0] = cpu_to_le32(0x00000028);
msg[1] = cpu_to_le32(0x00000018);
msg[2] = cpu_to_le32(0x00000000);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index a3eed90b6af0..23a80e656ddc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -172,6 +172,7 @@
#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001
#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001
+#define AMDGPU_VCN_CMD_FLAG_SESSION_CONTEXT_BUFFER 0x00100000
#define VCN_CODEC_DISABLE_MASK_AV1 (1 << 0)
#define VCN_CODEC_DISABLE_MASK_VP9 (1 << 1)
@@ -375,7 +376,9 @@ struct amdgpu_vcn_decode_buffer {
uint32_t valid_buf_flag;
uint32_t msg_buffer_address_hi;
uint32_t msg_buffer_address_lo;
- uint32_t pad[30];
+ uint32_t session_context_buffer_address_hi;
+ uint32_t session_context_buffer_address_lo;
+ uint32_t pad[28];
};
#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
--
2.25.1
