[PATCH Review 1/1] drm/amdgpu: Fix out of range

[Stanley . Yang]

The xcc index should be refer to xcc_mask, convert xcc_mask
to counts then calculate device instance.

Signed-off-by: Stanley.Yang <stanley.y...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 9053435488c5..cd833cd3ebd2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1076,19 +1076,21 @@ static void gfx_v9_4_3_xcc_unset_safe_mode(struct 
amdgpu_device *adev,
 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
 {
        int xcc_id;
+       int num_xcc, dev_inst;
        struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
 
-       for (xcc_id = 0; xcc_id < AMDGPU_MAX_RLC_INSTANCES; xcc_id++) {
-               if (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)
-                       continue;
-               reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, 
xcc_id)];
-               reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 
GET_INST(GC, xcc_id), regSCRATCH_REG0);
-               reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 
GET_INST(GC, xcc_id), regSCRATCH_REG1);
-               reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 
GET_INST(GC, xcc_id), regSCRATCH_REG2);
-               reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 
GET_INST(GC, xcc_id), regSCRATCH_REG3);
-               reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, 
xcc_id), regGRBM_GFX_CNTL);
-               reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, 
xcc_id), regGRBM_GFX_INDEX);
-               reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, 
xcc_id), regRLC_SPARE_INT);
+       num_xcc = NUM_XCC(adev->gfx.xcc_mask);
+       for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
+               dev_inst = GET_INST(GC, xcc_id);
+
+               reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[dev_inst];
+               reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, dev_inst, 
regSCRATCH_REG0);
+               reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, dev_inst, 
regSCRATCH_REG1);
+               reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, dev_inst, 
regSCRATCH_REG2);
+               reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, dev_inst, 
regSCRATCH_REG3);
+               reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, dev_inst, 
regGRBM_GFX_CNTL);
+               reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, dev_inst, 
regGRBM_GFX_INDEX);
+               reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, dev_inst, 
regRLC_SPARE_INT);
        }
 }
 
-- 
2.25.1